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Flash EEprom system

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0330455 (2002-12-26)
발명자 / 주소
  • Harari, Eliyahou
  • Norman, Robert D.
  • Mehrotra, Sanjay
출원인 / 주소
  • SanDisk Corporation
대리인 / 주소
    Parsons Hsue & de Runtz LLP
인용정보 피인용 횟수 : 28  인용 특허 : 156

초록

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected c

대표청구항

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected c

이 특허에 인용된 특허 (156)

  1. Hsia Yukun (Santa Ana CA) Rodgers Richard W. (Santa Ana CA), Adaptive WSI/MNOS solid state memory system.
  2. Harding Phillip A. (Palos Verdes Pennisula CA) Chong Carlos F. (Rancho Palos Verdes CA) Pockell Herman L. (Torrance CA), Address mapping for memory.
  3. Gould Robert T. M. (Downingtown PA), Apparatus and method for utilizing partially defective memory devices.
  4. Yamada Shinichiro (Tokyo JA) Ishida Akira (Tokyo JA) Mukai Hisakazu (Musashino JA), Apparatus for accessing an information storage device having defective memory cells.
  5. Dutton Patrick F. (Endicott NY), Apparatus for automatically correcting erroneous data and for storing the corrected data in a common pool alternate memo.
  6. Slakmon Gilbert (Paris FRX), Apparatus for detecting faulty sectors and for allocating replacement sectors in a magnetic disc memory.
  7. Hicks Ray (2605 Corunna Rd. Flint MI 48503-3362), Automated photographic apparatus.
  8. Awaya Tomoharu (Yokohama JPX) Fukushi Isao (Tokyo JPX), Bipolar-transistor type semiconductor memory device having redundancy configuration.
  9. McKenny Vernon G. (Carrollton TX) Taylor David L. (Carrollton TX), Block redundancy for memory array.
  10. Foster William R. (Ottawa CAX), Bubble memory disk emulation system.
  11. Naden Rex A. (Richardson TX), Bubble redundancy map storage using non-volatile semiconductor memory.
  12. Furuya Akihiko (Tokyo JPX) Kanamaru Kouiti (Tokyo JPX) Inoue Junichi (Tokyo JPX), Cache system used in a magnetic disk controller adopting an LRU system.
  13. Schrenk Hartmut (Haar DEX), Circuit having a data memory and addressing unit for reading, writing and erasing the memory.
  14. Cricchi ; James R. ; Brewer ; Joe E., Circuit producing a common clear signal for erasing selected arrays in a MNOS memory system.
  15. Ermolovich Thomas R. (Lexington MA) Stewart Robert E. (Stow MA) Leonard Judson S. (Acton MA) Cutler David N. (Nashua NH), Communications device for data processing system.
  16. Waite David P. (Alexandria VA) Riddell Horace G. (Chantilly VA), Communications network for communicating with computers provided with disparate protocols.
  17. Bosen Robert J. (Spanish Fork UT), Computer intercommunication system.
  18. Wozniak Stephen G. (San Jose CA), Controller for magnetic disc, recorder, or the like.
  19. Bonke Carl (Rancho Santa Margarita CA), Data disk defect handling using relocation ID fields.
  20. Sato Fumitaka (Oome JPX), Data processing system.
  21. Iijima Yasuo (Yokohama JPX), Data storage system having circuitry for dividing received data into sequential wards each stored in storage region iden.
  22. Spencer, David H.; Steiner, Marvin E.; Lang, Donald H., Defect tolerant memory.
  23. Hagiwara Takaaki (Kodaira JPX) Horiuchi Masatada (Koganei JPX) Kondo Ryuji (Kodaira JPX) Yatsuda Yuji (Kanagawa JPX) Minami Shinichi (Hachioji JPX), Defect-remediable semiconductor integrated circuit memory and spare substitution method in the same.
  24. Tuma George B. (Scotts Valley CA) Tuma Wade B. (Reno NV) Warne Robert E. (Markleeville CA), Disk emulation system.
  25. Rubinson Barry L. (Colorado Springs CO) Parenti Mark A. (Colorado Springs CO) Lary Richard F. (Colorado Springs CO) Gardner Edward A. (Colorado Springs CO), Disk format for secondary storage system.
  26. Hoffman Charles R. (Raleigh NC), Dynamic RAM with non-volatile back-up storage and method of operation thereof.
  27. LaVallee Russell W. (Poughkeepsie NY) Ryan Philip M. (Hopewell Junction NY) Sollitto ; Jr. Vincent F. (Rhinebeck NY), Dynamic replacement of defective memory words.
  28. Hansen Barry W. (Rochester MN) Romon Raymond F. (Oronoco MN), Dynamic terminal address allocation by the terminal itself in a data processing system.
  29. Lambrache Emil (San Jose CA) Smarandoiu George (San Jose CA), EEPROM array with flash-like core.
  30. Baglee David A. (Houston TX) Smayling Michael C. (Missouri City TX), EEPROM memory having extended life.
  31. Yamamura Sigeyuki (Tenri JPX) Nakamura Yasuhide (Yamatokoriyama JPX), Elecetronic cash register.
  32. Harari ; Eliyahou, Electrically erasable non-volatile semiconductor memory.
  33. Giebel Burkhard (Denzlingen DEX), Electrically programmable semiconductor memory showing redundance.
  34. Pape David D. (Framingham MA), Electronic imaging camera utilizing EPROM memory.
  35. Lavelle Gary E. (Avon CT), Electronic locking system.
  36. Sansone Ronald P. (Weston CT) Stelben John J. (Greenwich CT), Electronic postage meter non-volatile memory systems having human visually readable and machine stored data.
  37. Rudnick Paul J. (Castro Valley CA) Toldalagi Paul M. (Danville CA) Neff Harlan (Castro Valley CA), Electronic sports information retrieval device.
  38. d\Alayer de Costemore d\Arc Stephane M. (Ways BEX), Electronic still camera with individual non-volatile memory units.
  39. Wayama Yukio (Numazu JPX) Miyajima Naoto (Shizuoka JPX) Shinozaki Michio (Numazu JPX) Yashima Kazunari (Numazu JPX), Emulation device for converting magnetic disc memory mode signal from computer into semiconductor memory access mode sig.
  40. Mehrotra Sanjay (San Jose CA) Perlegos Gust (Fremont CA), Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array.
  41. Beardsley Brent C. (Tucson AZ) Canon Michael D. (San Jose CA) Easton Malcolm C. (San Jose CA) Hartung Michael H. (Tucson AZ) Howard John H. (San Jose CA) Vosacek Robert H. (Tucson AZ), Fast write operations.
  42. Choate William Clay (Dallas TX), Fault-tolerant cell addressable array.
  43. Thomas Michael E. (201 S. 4th St. #629 San Jose CA 95112), Ferroelectric storage device used in place of a rotating disk drive unit in a computer system.
  44. Harari Eliyahou (104 Auzerais Ct. Los Gatos CA 95030), Flash EEPROM memory systems having multistate storage cells.
  45. Harari Eliyahou (Los Gatos CA) Norman Robert D. (San Jose CA) Mehrotra Sanjay (Milpitas CA), Flash EEprom system.
  46. Harari Eliyahou ; Norman Robert D. ; Mehrotra Sanjay, Flash EEprom system.
  47. Harari, Eliyahou; Norman, Robert D.; Mehrotra, Sanjay, Flash EEprom system.
  48. Harari Eliyahou (Los Gatos CA) Norman Robert D. (San Jose CA) Mehrotra Sanjay (Milpitas CA), Flash eeprom system.
  49. Harari Eliyahou (Los Gatos CA) Norman Robert D. (San Jose CA) Mehrotra Sanjay (Milpitas CA), Flash eeprom system with defect handling.
  50. Vermesse Bernard (L\Hay les Roses FRX), Franking machine providing a periodic historical trail.
  51. Brewer Joe E. (Severna Park MD), High-density memory with non-volatile storage array.
  52. Harari Eliyahou (2320 Friars La. Los Altos CA 94022), Highly compact EPROM and flash EEPROM devices.
  53. Watanabe Hiroshi (Kokubunji JPX), IC card.
  54. Yorimoto Yoshikazu (Matsudo JPX) Takahashi Masashi (Tokyo JPX), IC card.
  55. Watanabe Hiroshi (Kokubunji JPX), IC card having state marker for record access.
  56. Daughters Turpen A. (Pinole CA) McGinnis Patricia A. (San Anselmo CA), IC card system.
  57. Watanabe Mikio (Tokyo JPX) Nishi Seiki (Tokyo JPX), Image data recording apparatus for storing image data with a recording-finished code and a recording sequence code.
  58. Suzuki Noriyuki (Tokyo JPX) Asai Hironobu (Tokyo JPX), In-circuit emulator.
  59. Hosotani Osamu (Hyogo JPX) Kawauchi Koichi (Hyogo JPX) takahashi Naoki (Hyogo JPX), Information processing unit.
  60. Satoh Isao (Neyagawa JPX) Fukushima Yoshihisa (Osaka JPX), Information recording and reproducing apparatus with detection and management of defective sectors.
  61. Giebel Burkhard (Denzlingen DEX) Fischer Thomas (Umkirch DEX), Integrated matrix of nonvolatile, reprogrammable storage cells.
  62. Rosini Paolo (Monza ITX) Finaurini Roberto (Ancona ITX) Gaibotti Maurizio (Barlassina ITX), Integrated structure microcomputer provided with non-volatile RAM memory.
  63. Wawersig Jrgen (Munich DEX) Kantz Dieter (Munich DEX), Integrated write/read memory.
  64. Burgess, Bradley G., Intelligent electrically erasable, programmable read-only memory with improved read latency.
  65. Gee Lubin (Santa Clara CA) Cheng Pearl (Sunnyvale CA) Bobra Yogendra (Santa Clara CA) Mehta Rustam (Sunnyvale CA), Intelligent electrically programmable and electrically erasable ROM.
  66. Birkner David A. (Wellesley MA) Sankey Mark A. (Lexington MA), Interface adaptor emulating magnetic tape drive.
  67. Vermesse Bernard (L\Hay les Roses FRX), Limited write non-volatile memory and a franking machine making use thereof.
  68. Berger Blaine H. (Longmont CO) Smith Bret P. (Longmont CO), Maintaining duplex-paired storage devices during gap processing using of a dual copy function.
  69. Martinez Maria N. (Prestbury IL), Management of defects in storage media.
  70. Kulakowski John E. (Tucson AZ) Means Rodney J. (Tucson AZ), Managing data storage space on large capacity record media.
  71. Kressel Henry (Elizabeth NJ) Hsu Sheng T. (Lawrenceville NJ), Memory array with redundant elements.
  72. Nakagawa Katsuya (Kyoto JPX), Memory cartridge bank selecting apparatus.
  73. Singh Shanker (Fishkill NY) Singh Vijendra P. (Saratoga CA), Memory correction scheme using spare arrays.
  74. Ishida ; Akira, Memory device.
  75. Simon Francois Y. (Raleigh NC), Memory interface for communicating between two storage media having incompatible data formats.
  76. Das ; Santanu, Memory sparing arrangement.
  77. Hamilton Stephen P. (Midland TX) Hunter Arthur C. (Lubbock TX), Memory system having a common interface.
  78. Moxley David C. (Irmo SC), Memory system having an alternate memory.
  79. Bond George L. (Fishkill NY) Satya Akella V. S. (Wappingers Falls NY), Memory system with selective assignment of spare locations.
  80. Pelley ; III Perry H. (Austin TX) Morton Bruce L. (Round Rock TX), Memory with redundancy and predecoded signals.
  81. Bastian Arlon L. (Pima County AZ) Goldfeder Marc E. (Tucson AZ) Hartung Michael H. (Pima County AZ), Method and apparatus for limiting data occupancy in a cache.
  82. Halfhill Martin O. (San Jose CA) Jacques James O. (Limerick PA), Method and apparatus for recording data without recording on defective areas of a data recording medium.
  83. Robinson Don M. (Santa Clara County CA) Davenport Henry E. (Santa Cruz County CA), Method for mapping around defective sectors in a disc drive.
  84. Robinson Don M. (Santa Clara County CA) Davenport Henry E. (Santa Cruz County CA), Method for mapping around defective sectors in a disc drive.
  85. Schrenk Hartmut (Haar DEX), Method for operating a user memory designed a non-volatile write-read memory, and arrangement for implementing the metho.
  86. Picon Joaquin (St. Laurent du Var FRX) Poiraud Clement Y. G. (Cagnes sur Mer FRX) Sazbon-Natansohn Daniel (Villeneuve Loubet FRX), Method for storing the control code of a processor allowing effective code modification and addressing circuit therefor.
  87. Foster Mark J. (Stevensville MI) Rajaram Babu (St. Joseph MI) Olson Anthony M. (Stevensville MI), Method of combining lower order and translated upper order bits to address ROM within a range reserved for other devices.
  88. Nozawa Masafumi (Minami-ashigara JPX) Miyazaki Michio (Odawara JPX), Method of controlling storage device.
  89. Carlson George M. (Sugarland TX) O\Hagan Michael (Dallas TX), Microprocessor based system for the development and emulation of programmable calculator control read only memory softwa.
  90. Koike Hideharu (Yokohama JPX), Multi-bit-per-cell read only memory circuit.
  91. Mehrotra Sanjay (Milpitas CA) Harari Eliyahou (Los Gatos CA) Lee Winston (San Francisco CA), Multi-state EEprom read and write circuits and techniques.
  92. Mehrotra Sanjay (Milpitas CA) Harari Eliyahou (Los Gatos CA) Lee Winston (San Francisco CA), Multi-state EEprom read and write circuits and techniques.
  93. Harari Eliyahou ; Norman Robert D. ; Mehrotra Sanjay, Multi-state flash EEprom system with cache memory.
  94. Yoshimatsu Kenzo (Kawasaki JPX), Multi-use portable electronic device.
  95. Needham David B. (Kissimmee FL), Multimedia interface device and method.
  96. Stark Moshe (Haifa ILX), Multiple bit read-only memory cell and its sense amplifier.
  97. Goodman James B. (9600 Golf Lakes Trail ; Apt. 2010 Dallas TX 75231), Multiple configuration memory circuit.
  98. Terashima Yoshiyuki (Nagano JPX), Non-volatile memory circuit.
  99. Mackiewicz Ralph E. (Madison Heights MI) Kuhn Michael A. (Royal Oak MI), Non-volatile memory device for a programmable controller.
  100. Terada Yasushi (Hyogo JPX) Nakayama Takeshi (Hyogo JPX) Kobayashi Kazuo (Hyogo JPX), Non-volatile semiconductor memory device.
  101. Tanaka Tomoharu (Yokohama JPX) Momodomi Masaki (Yokohama JPX) Kato Hideo (Kawasaki JPX) Nakai Hiroto (Yokohama JPX) Tanaka Yoshiyuki (Yokohama JPX) Shirota Riichiro (Fujisawa JPX) Aritome Seiichi (Ka, Non-volatile semiconductor memory device and memory system using the same.
  102. Kroll Paul C. (New Milford CT) Chang Sung S. (Stamford CT), Nonvolatile memory protection arrangement for electronic postage meter system having plural nonvolatile memories.
  103. Brookner George M. (Norwalk CT) Soderberg John H. (Stratford CT), Nonvolatile memory unlock for an electronic postage meter.
  104. Hijiya Shinpei (Sagamihara JPX) Nozaki Takao (Yokohama JPX) Ito Takashi (Kawasaki JPX) Ishikawa Hajime (Yokohama JPX), Nonvolatile semiconductor memory device.
  105. Heath Chester A. (Boca Raton FL), Peripheral interface adapter circuit for use in I/O controller card having multiple modes of operation.
  106. Suzuki Yasuo (Yokohama JPX) Hirao Hiroshi (Kawasaki JPX) Suzuki Yasuaki (Kawasaki JPX), Plural-bit-per-cell read-only memory.
  107. Iijima Yasuo (Yokohama JPX), Portable electronic device with garbage collection function.
  108. Iijima Yasuo (Yokohama JPX), Portable electronic device with plural memory areas.
  109. Jiang Ching-Lin (Dallas TX) Lee Robert D. (Denton TX), Portable, non-volatile read/write memory module.
  110. Kreifels Jerry A. (Citrus Heights CA) Baker Alan (Fair Oaks CA) Hoekstra George (Santa Clara CA) Kynett Virgil N. (El Dorado Hills CA) Wells Steven (Orangevale CA) Winston Mark (El Dorado Hills CA), Processor controlled command port architecture for flash memory.
  111. Kreifels Jerry A. (Citrus Heights CA) Baker Alan (Fair Oaks CA) Hoekstra George (Santa Clara CA) Kynett Virgil N. (El Dorado Hills CA) Wells Steven (Orangevale CA) Winston Mark (El Dorado Hills CA), Program/erase selection for flash memory.
  112. Smith Teresa B. (Columbia MD) Smith Philip C. (Columbia MD), Programmable redundancy circuit.
  113. , Pseudo-erasable and rewritable write-once optical disk memory system.
  114. Moench Jerry D. (Austin TX), ROM Storage location having more than two states.
  115. Liou Jiunn-Yau (San Jose CA) Lee May-Lin (Cupertino CA) Kok Moon S. (Milpitas CA) Yu James (San Jose CA) Tam Aloysius T. (Sunnyvale CA), Random access memory device with block reset.
  116. Kobatake Hiroyuki (Tokyo JPX), Read only semiconductor memory having multiple bit cells.
  117. Ip William W. (San Jose CA) Perlegos Gust (Fremont CA), Redundancy circuit for use in a semiconductor memory array.
  118. Lim Hyung-Kyu (Suwon KRX) Do Jae-Yeong (Dongjak CA KRX) Mehta Rustam (Sunnyvale CA), Redundancy circuit for use in a semiconductor memory device.
  119. Tsang Frederick (Saratoga CA) Kannal Gregory A. (Mountain View CA) Hoff ; Jr. Marcian E. (Sunnyvale CA), Redundant memory circuit.
  120. Nibby ; Jr. Chester M. (Peabody MA) Goldin Reeni (Somerville MA) Andrews Timothy A. (Arlington MA), Remap method and apparatus for a memory system which uses partially good memory devices.
  121. Logan Donald G. (Blackstone MA), Remapping defects in a storage system through the use of a tree structure.
  122. Walker Christopher P. H. (Bristol CO GB2) Wilson Peter J. (Colorado Springs CO), Repairable ROM array.
  123. Anderl Ewald C. (Middletown NJ) Frankel Oren (Ocean Township ; Monmouth County NJ) Zahavi Avi (Highland Park NJ), Security file system and method for securing data in a portable data carrier.
  124. Watanabe Hiroshi (Kokubunji JPX), Selectable data readout IC card.
  125. Anderson James M. (Campbell CA) Knight ; III Thomas S. (Sunnyvale CA) Kitagawa Dennis T. (San Jose CA) Rey Ernesto (San Jose CA), Self repairing bulk memory.
  126. Fukuda Joji (Yokohama JPX) Okubo Yutaka (Atsugi JPX), Semiconductor RAM that is accessible in magnetic disc storage format.
  127. Nakamura Hideo (Tokyo JPX) Sawase Terumi (Sayama JPX), Semiconductor integrated circuit with nonvolatile memory.
  128. Nakamura Hideo (Tokyo JPX) Sawase Terumi (Sayama JPX), Semiconductor integrated circuit with nonvolatile memory.
  129. Nakamura Hideo (Tokyo JPX) Sawase Terumi (Sayama JPX), Semiconductor integrated circuit with nonvolatile memory.
  130. Fujita Kenji (Odawara JPX) Nakao Toshiyuki (Hadano JPX) Yamagata Hirotsugu (Odawara JPX) Saze Nobuyuki (Odawara JPX), Semiconductor memory.
  131. Fukuda Minoru (Tateno JPX) Takahashi Hideaki (Kogenei NY JPX) Sugiura June (Troy NY) Tsuchiya Fumio (Kodaira JPX) Kihara Toshimasa (Tachikawa JPX), Semiconductor memory.
  132. Kobayashi Junichi (Suwa JPX) Tateno Hiroaki (Suwa JPX) Ikeda Masayuki (Suwa JPX) Samejima Shogo (Suwa JPX), Semiconductor memory configured to emulate floppy and hard disk magnetic storage based upon a determined storage capacit.
  133. Sasaki Toshio (Tokyo JPX) Aoki Masakazu (Tokorozawa JPX) Horiguchi Masashi (Kokubunji JPX) Nakagome Yoshinobu (Hachioji JPX) Ikenaga Shinichi (Kokubunji JPX) Masuhara Toshiaki (Tokyo JPX), Semiconductor memory device.
  134. Takemae Yoshihiro (Tokyo JPX), Semiconductor memory device having error correction function and incorporating redundancy configuration.
  135. Haeusele Hans (Munich DEX), Semiconductor memory formed of memory modules with redundant memory areas.
  136. Tayler Gerald E. (Berthoud CO) Wagner Robert E. (Tucson AZ), Sequentially processing data in a cached data storage system.
  137. Hewitt Kent D. (Tempe AZ) Alexander Samuel E. (Gilbert AZ) Fisher Richard J. (Phoenix AZ), Serial EEPROM device and associated method for reducing data load time using a page mode write cache.
  138. Lienau Richard M. (2404 Sebald Ave. Redondo Beach CA 90278) Pope Kenneth E. (Wagoner OK), Sheet random access memory.
  139. Healy Leonard D. (Orlando FL), Simulator interface system.
  140. Balch Kris S. (San Diego CA), Solid state electronic emulator of a multiple track motor driven rotating magnetic memory.
  141. Kunstadt George H. (4450 La Barca Tarzana CA 91356), Solid state mass memory system compatible with rotating disc memory equipment.
  142. Muller Hans R. (Redmond WA), Solid state memory for aircraft flight data recorder systems.
  143. Norman Robert D. (San Jose CA) Lofgren Karl M. J. (Newport Beach CA) Stai Jeffrey D. (Placentia CA) Gupta Anil (Irvine CA) Mehrotra Sanjay (Milpitas CA), Solid state memory system including plural memory chips and a serialized bus.
  144. Sundet James W. (Chippewa Falls WI), Solid state storage device.
  145. Iida Norihiko (Tokyo JPX) Kawata Kazuhide (Tokyo JPX), System for controlling a nonvolatile memory having a data portion and a corresponding indicator portion.
  146. Carlton James E. (San Jose CA) Schaeuble Werner J. (San Jose CA), System for controlling a serial data channel with a microprocessor.
  147. Ogasawara Nobuo (Kawasaki JPX), System for data field area acquisition in IC card for multiple services.
  148. Muller Arno (Westport CT), System for limiting access to non-volatile memory in electronic postage meters.
  149. Ogasawara Nobuo (Kawasaki JPX), System for permitting access to data field area in IC card for multiple services.
  150. Ryan Philip M. (Hopewell Junction NY), System for updating error map of fault tolerant memory.
  151. Danielson Arvin D. (Cedar Rapids IA) Kubler Joseph J. (Nederland CO) Durbin Dennis A. (Cedar Rapids IA) Morris Michael D. (Cedar Rapids IA) Cargin ; Jr. Keith K. (Cedar Rapids IA), System including multiple device communications controller which coverts data received from two different customer trans.
  152. Hirtle Allen C. (Needham MA), Table driven emulation system.
  153. White Barry B. (Boulder CO), Virtual storage system and method.
  154. Hoff ; Jr. Marcian E. (Sunnyvale CA), Wafer scale integration system.
  155. Schrenk Hartmut (Haar DEX), Word-by-word electrically reprogrammable nonvolatile memory.
  156. Tigelaar Howard L. (Allen TX) Mitchell Allan T. (Garland TX) Riemenschneider Bert R. (Murphy TX) Paterson James L. (Richardson TX), X-cell EEPROM array.

이 특허를 인용한 특허 (28)

  1. Tran,Dat; Ponnuru,Kiran; Chen,Jian; Lutze,Jeffrey W.; Wan,Jun, Comprehensive erase verification for non-volatile memory.
  2. Tran,Dat; Ponnuru,Kiran; Chen,Jian; Lutze,Jeffrey W.; Wan,Jun, Comprehensive erase verification for non-volatile memory.
  3. Tran,Dat; Ponnuru,Kiran; Chen,Jian; Lutze,Jeffrey W.; Wan,Jun, Comprehensive erase verification for non-volatile memory.
  4. Lai, Ming-Shiang; Tsai, Chung-Hung, Embedded system for compensating setup time violation and method thereof.
  5. Tai,Shih Chieh; Wu,Chien Hung, Flash memory data access method and configuration employing logical-to-virtual and virtual-to-physical sector mapping.
  6. Jo,Seong Kue, Flash memory device for performing bad block management and method of performing bad block management of flash memory device.
  7. Sibigtroth,James M.; Espinor,George L.; Morton,Bruce L., Memory bit line segment isolation.
  8. De Santis, Luca; Pilolli, Luigi, Memory device distributed controller system.
  9. De Santis,Luca; Pilolli,Luigi, Memory device distributed controller system.
  10. Santis, Luca De; Pilolli, Luigi, Memory device distributed controller system.
  11. Moogat, Farookh; Cernea, Raul-Adrian; Tsao, Shou-Chang; Tseng, Tai-Yuan, Method for column redundancy using data latches in solid-state memories.
  12. Moogat,Farookh; Cernea,Raul Adrian; Tsao,Shouchang; Tseng,Tai Yuan, Method for column redundancy using data latches in solid-state memories.
  13. Ho,Chunchun, Method for recycling flash memory.
  14. Cernea,Raul Adrian, Method for remote redundancy for non-volatile memory.
  15. Hodder,Leonard B., Method of correcting NAND memory blocks and to a printing device employing the method.
  16. Litsyn, Simon; Alrod, Idan; Sharon, Eran; Murin, Mark; Lasser, Menahem, Method of error correction in MBC flash memory.
  17. Litsyn, Simon; Alrod, Idan; Sharon, Eran; Murin, Mark; Lasser, Menahem, Method of error correction in MBC flash memory.
  18. De Santis, Luca; Pilolli, Luigi, Methods for operating a distributed controller system in a memory device.
  19. Cernea, Raul Adrian, Non-volatile memory with redundancy data buffered in remote buffer circuits.
  20. Cernea, Raul-Adrian, Non-volatile memory with redundancy data buffered in remote buffer circuits.
  21. Cernea,Raul Adrian, Non-volatile memory with redundancy data buffered in remote buffer circuits.
  22. Camp, Charles J.; Frost, Holloway H., Reduction of read disturb errors.
  23. Camp, Charles J.; Frost, Holloway H., Reduction of read disturb errors.
  24. Camp, Charles J.; Frost, Holloway H., Reduction of read disturb errors in NAND FLASH memory.
  25. Sato,Tsunehiro; Hayashi,Kiyotaka, Semiconductor device.
  26. Nagai,Takeshi; Haga,Ryo, Setting method of chip initial state.
  27. Tran,Dat; Ponnuru,Kiran; Chen,Jian; Lutze,Jeffrey W.; Wan,Jun, Systems for comprehensive erase verification in non-volatile memory.
  28. Tran,Dat; Ponnuru,Kiran; Chen,Jian; Lutze,Jeffrey W.; Wan,Jun, Systems for comprehensive erase verification in non-volatile memory.
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