IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0337818
(2003-01-08)
|
우선권정보 |
JP-0048656 (2001-02-23) |
발명자
/ 주소 |
- Watanabe, Masaki
- Murase, Kentaro
- Noda, Takuya
- Watanabe, Kazuhiro
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
55 인용 특허 :
1 |
초록
▼
An image sensor, a voice sensor, an auxiliary sensor part (infrared sensor, etc.), a total analyzing part, and an application communicate with each other through data/control signal communication units. Each sensor provides feedback on its signal detection results and control information used by the
An image sensor, a voice sensor, an auxiliary sensor part (infrared sensor, etc.), a total analyzing part, and an application communicate with each other through data/control signal communication units. Each sensor provides feedback on its signal detection results and control information used by the other sensors for determining a range of a detection target and a detection sensitivity at a time of subsequent signal acquisition, to the other sensors through the communication units. The total analyzing part investigates whether or not there is inconsistency among the results detected by the respective sensors, and provide control information to each sensor. Each sensor determines a range of a signal detection target and a detection sensitivity based on the obtained information, and acquires a signal in accordance with the determination.
대표청구항
▼
An image sensor, a voice sensor, an auxiliary sensor part (infrared sensor, etc.), a total analyzing part, and an application communicate with each other through data/control signal communication units. Each sensor provides feedback on its signal detection results and control information used by the
An image sensor, a voice sensor, an auxiliary sensor part (infrared sensor, etc.), a total analyzing part, and an application communicate with each other through data/control signal communication units. Each sensor provides feedback on its signal detection results and control information used by the other sensors for determining a range of a detection target and a detection sensitivity at a time of subsequent signal acquisition, to the other sensors through the communication units. The total analyzing part investigates whether or not there is inconsistency among the results detected by the respective sensors, and provide control information to each sensor. Each sensor determines a range of a signal detection target and a detection sensitivity based on the obtained information, and acquires a signal in accordance with the determination. a finite state machine that inputs a signal from the first phase detector and outputs at least one control bit to the tunable buffer dependent on the signal from the first phase detector. 6. The integrated circuit of claim 5, wherein an output from the finite state machine is connected to a control bus. 7. The integrated circuit of claim 6, wherein the tunable buffer comprises: a transistor stack, wherein the transistor stack contributes current to an output of the tunable buffer dependent on the control bus. 8. The integrated circuit of claim 6, wherein the transistor stack decreases current to an output of the tunable buffer dependent on the control bus. 9. The integrated circuit of claim 7, wherein the transistor stack comprises a transistor having an input operatively connected to a control bit on the control bus. 10. A method for decreasing clock skew, comprising: comparing a phase difference between a reference clock signal and a feedback signal; responsive to the phase difference between the reference clock signal and the feedback signal, adjusting a delay of a first clock delay circuit operatively connected to a portion of a clock grid, wherein the feedback signal is operatively connected to the portion of the clock grid; comparing a phase difference between the feedback signal and another feedback signal, wherein the another feedback signal is operatively connected to another portion of the clock grid; and responsive to the phase difference between the feedback signal and the another feedback signal, adjusting a delay of a second clock delay circuit operatively connected to the another portion of the clock grid. 11. The method of claim 10, further comprising: generating pulses on an up/down signal to a finite state machine dependent on the phase difference between the reference clock signal and the feedback signal; generating at least one control bit to a buffer in the first clock delay circuit in response to generating pulses on the up/down signal; and driving a signal on the portion of the clock grid based on the at least one control bit. 12. An integrated circuit, comprising: means for comparing a phase difference between a reference clock signal and a feedback signal; means for adjusting a delay of a first clock delay circuit operatively connected to a portion of a clock grid dependent on the means for comparing the phase difference between the reference clock signal and the feedback signal, wherein the feedback signal is operatively connected to the portion of the clock grid; means for comparing a phase difference between the feedback signal and another feedback signal, wherein the another feedback signal is operatively connected to another portion of the clock grid; and means for adjusting a delay of a second clock delay circuit operatively connected to the another portion of the clock grid dependent on the means for comparing the phase difference between the feedback signal and the another feedback signal.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.