초록 ▼

A processor controlled implantable cardiac stimulation device may be placed into a shelf mode for extending the shelf life of the device. The device includes a real time clock circuit, a watch dog timer circuit having a duty cycle, a telemetry circuit capable of operation in either an active mode or

A processor controlled implantable cardiac stimulation device may be placed into a shelf mode for extending the shelf life of the device. The device includes a real time clock circuit, a watch dog timer circuit having a duty cycle, a telemetry circuit capable of operation in either an active mode or a standby mode, and ancillary circuits that sense cardiac activity and provides stimulation pulses to a heart. The device includes a power source for providing power to all of the circuits of the device and a shelf mode circuit that places the device into the shelf mode. The shelf mode circuit disables power to the ancillary circuits, decreases the duty cycle of the watch dog timer, sets the processor into a static state, and sets the telemetry circuit to the standby mode. The shelf mode circuit places the device into the shelf mode in response to shelf mode commands received by the telemetry circuit to set the device from an active powered mode to the shelf mode.

대표청구항 ▼

A processor controlled implantable cardiac stimulation device may be placed into a shelf mode for extending the shelf life of the device. The device includes a real time clock circuit, a watch dog timer circuit having a duty cycle, a telemetry circuit capable of operation in either an active mode or

A processor controlled implantable cardiac stimulation device may be placed into a shelf mode for extending the shelf life of the device. The device includes a real time clock circuit, a watch dog timer circuit having a duty cycle, a telemetry circuit capable of operation in either an active mode or a standby mode, and ancillary circuits that sense cardiac activity and provides stimulation pulses to a heart. The device includes a power source for providing power to all of the circuits of the device and a shelf mode circuit that places the device into the shelf mode. The shelf mode circuit disables power to the ancillary circuits, decreases the duty cycle of the watch dog timer, sets the processor into a static state, and sets the telemetry circuit to the standby mode. The shelf mode circuit places the device into the shelf mode in response to shelf mode commands received by the telemetry circuit to set the device from an active powered mode to the shelf mode. e titanium metal layer covering the access-node junction at the bottom of the contact opening to titanium silicide. 4. A method for fabricating an integrated circuit, said method comprising: forming a plurality of field-effect transistor gates and a gate interconnect on a horizontal substrate; forming at least two word lines on the substrate, at least one word line having a lower surface which is dielectrically insulated from the substrate by a gate dielectric layer, said at least two word lines each having an upper surface and sidewalls which are covered by a word line isolation layer comprising a first dielectric material; depositing an interlevel dielectric layer, said interlevel dielectric layer comprising a second dielectric material, said second dielectric material being selectively etchable with respect to said first dielectric material; etching a plurality of vertically oriented contact openings having a sidewall and a bottom through said interlevel dielectric layer, each contact opening of said plurality of contact openings having the bottom thereof exposing a junction in the substrate adjacent at least one word line of the at least two word lines, each of said contact openings at least partially overlapping the word line isolation layer on the sidewall of said at least one adjacent word line, each vertically oriented contact opening having a height to width ratio of at least greater than 5 to 1; lining the sidewall and the bottom of each contact opening with a titanium metal layer to provide a titanium metal lined contact opening; lining each titanium metal lined contact opening with a titanium nitride layer to provide a double lined contact opening; forming a tungsten metal plug within each double lined contact opening; and forming a plurality of metal digit lines, each digit line contacting a plurality of tungsten metal plugs. 5. The method of claim 4, further comprising: planarizing the interlevel dielectric layer prior to etching the plurality of contact openings. 6. The method of claim 4, further comprising: annealing the titanium metal layer using an elevated temperature converting at least a portion of the titanium metal layer overlying the substrate at the bottom of the contact opening to titanium silicide. 7. The method of claim 4, wherein said integrated circuit is a dynamic random access memory array and the method further comprises: fabricating a stacked capacitor for each memory cell within the memory array. 8. The method of claim 7, wherein the interlevel dielectric layer is deposited to a depth covering each stacked capacitor. 9. A process for manufacturing an array of dynamic random access memory cells on a silicon substrate, said process comprising: forming a field oxide pattern on channel stop regions of the substrate as isolation areas; forming a gate dielectric layer on other regions of the substrate as active areas; forming a triple-layer sandwich having a polycrystalline silicon layer in contact both with an upper surface of the gate dielectric layer and an upper surface of the field oxide pattern, a refractory metal silicide layer on the polycrystalline silicon layer, and a silicon nitride layer on the silicide layer; forming word lines from the triple-layer sandwich including: forming a mask pattern on the sandwich; etching the sandwich with an anisotropic plasma etch, each of said word lines having vertical sidewalls, each of said word lines forming an access transistor gate where it overlies the gate dielectric layer, and forming an access transistor gate interconnect where it overlies field oxide, forming access transistor source/drain regions on opposite sides of the word lines within the active areas; forming silicon nitride spacers on the sidewalls of each word line; forming a stacked capacitor for each memory cell, each capacitor being electrically coupled to a source/drain region thereby forming a storage-node junction; depositing an interleve l dielectric layer covering each stacked capacitors; anisotropically etching digit line contact openings through the interlevel dielectric layer to the underlying source/drain regions thereby forming access-node junctions, each of said access-node junctions being shared by a pair of adjacent access transistors, said digit line contact openings being self-aligned to a gate sidewall spacer of each transistor of each adjacent access transistor pair, none of said contact openings exposing one of the polycrystalline silicon layer or the silicide layer which comprise a gate of an adjacent transistor, each digit line contact opening having a height to width ratio of at least greater than 5 to 1; depositing a titanium metal layer via chemical vapor deposition said titanium metal layer lining each contact opening and covering an exposed source/drain region at a bottom of each opening; depositing a titanium nitride layer via chemical vapor deposition, said titanium nitride layer covering the titanium metal layer; depositing a tungsten layer via chemical vapor deposition filling the contact openings; removing a portion of the titanium metal layer, a portion of the titanium nitride layer and a portion of the tungsten layer from an upper surface of the interlevel dielectric layer to leave a tungsten plug within each contact opening; and forming metal interconnect lines on an upper surface of the interlevel dielectric layer, each interconnect line making contact to a plurality of tungsten plugs. 10. The process of claim 9, further comprising: planarizing the interlevel dielectric layer prior to etching the digit line contact openings. 11.The process of claim 9, further comprising: annealing the titanium metal layer at an elevated temperature converting at least a portion of the titanium metal layer which overlies the silicon substrate at the bottom of the contact opening to titanium silicide.