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A flight display for use in an avionics system has a visual display format to show an enhanced vertical situation of an aircraft. Included is a vertical terrain profile display that displays terrain in front of the aircraft over a selected range and a selected swathe width. The vertical terrain prof

A flight display for use in an avionics system has a visual display format to show an enhanced vertical situation of an aircraft. Included is a vertical terrain profile display that displays terrain in front of the aircraft over a selected range and a selected swathe width. The vertical terrain profile display shows a side-on terrain profile view with a digital display of the selected swathe width and a display of range in front of the aircraft. A plan view of the aircraft position is included that shows swathe lines on either side of an aircraft to show the selected swathe width. A means for selecting the swathe width by the pilot is provided. The flight display the vertical terrain profile display may be changed into a end-on vertical terrain profile view over the selected swathe width. The end-on terrain profile view has a digital display of the selected range and a digital display of the selected swathe width on each side of the aircraft.

대표청구항 ▼

A flight display for use in an avionics system has a visual display format to show an enhanced vertical situation of an aircraft. Included is a vertical terrain profile display that displays terrain in front of the aircraft over a selected range and a selected swathe width. The vertical terrain prof

A flight display for use in an avionics system has a visual display format to show an enhanced vertical situation of an aircraft. Included is a vertical terrain profile display that displays terrain in front of the aircraft over a selected range and a selected swathe width. The vertical terrain profile display shows a side-on terrain profile view with a digital display of the selected swathe width and a display of range in front of the aircraft. A plan view of the aircraft position is included that shows swathe lines on either side of an aircraft to show the selected swathe width. A means for selecting the swathe width by the pilot is provided. The flight display the vertical terrain profile display may be changed into a end-on vertical terrain profile view over the selected swathe width. The end-on terrain profile view has a digital display of the selected range and a digital display of the selected swathe width on each side of the aircraft. which converts an analog test output from said D/A converter circuit of said semiconductor integrated circuit to be tested into a digital test output; and measured data memory for storing the digital test output from said A/D converter circuit of said semiconductor integrated circuit to be tested and said digital test output from said testing A/D converter circuit, wherein a result of analysis of said each digital test outputs stored in said measured data memory, the analysis being performed by said analysis section, is sent to said external controller. 2. The apparatus for testing a semiconductor integrated circuit according to claim 1, wherein said external controller is a tester. 3. The apparatus for testing a semiconductor integrated circuit according to claim 1, wherein said memory having stored therein said test requirement table is incorporated in said analysis section. 4. The apparatus for testing a semiconductor integrated circuit according to claim 1, wherein said test ancillary device comprises: a test analysis table having a memory address table for setting an address of the measured data memory in which digital test outputs are stored for a corresponding numeric code; a computation method table having stored therein information about computation methods corresponding to respective numeric codes; and a test specification table in which specification evaluation values corresponding to the respective numeric codes are stored, wherein when an analysis start instruction is received from said external controller along with a numeric code, a predetermined digital test output is read from said memory address table; a corresponding computation method is read from the computation method table, thereby computing a characteristic parameter of said A/D converter circuit of said semiconductor integrated circuit to be tested and a characteristic parameter of said D/A converter circuit of the same; a result of computation is compared with a specification evaluation value corresponding to the numeric code read from said test specification table, thus evaluating a specification; and a result of evaluation is sent to said external controller. 5. The apparatus for testing a semiconductor integrated circuit according to claim 4, wherein said characteristic parameters correspond to a differential linearity and an integral nonlinearity error. 6. The apparatus for testing a semiconductor integrated circuit according to claim 4, wherein transmission information for sending a digital test output is provided in said test analysis table; and, when a numeric code corresponding to transmission information is sent to said test ancillary device from said external controller, said test ancillary device reads a corresponding digital test output from said measured data memory, and the digital test output is sent to said external controller. 7. The apparatus for testing a semiconductor integrated circuit according to claim 6, wherein the numeric code to be used for selecting transmission information is formed by combination of a code representing details of a test and a code to be used for selecting transmission information. 8. A method for testing a semiconductor integrated circuit comprising, a test circuit board configured to transmit signals to and receive signals from a semiconductor integrated circuit to be tested wherein the semiconductor integrated circuit comprises an A/D converter circuit to convert analog signals to digital signals and a D/A converter circuit to convert digital signals to analog signals, the methods comprising the steps of: assigning a numeric code to each one of a test requirement stored in a test requirement table for tabulating hardware requirements for conducting test on said semiconductor integrated circuit to be tested; reading a test requirement corresponding to one of said numeric codes from said test requirement table; outputting a digital test signal on the basis of said test requirement rea