IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0473209
(1999-12-27)
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발명자
/ 주소 |
- Hussain, Zahid
- Mech, Radomir
- Tommasi, Gianpaolo
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
13 인용 특허 :
7 |
초록
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A graphics geometry cache. The basic idea of one embodiment in accordance with the present invention is to utilize a graphics geometry cache together with a graphics pipeline. The graphics geometry cache is a relatively small cache (e.g., 128 entries) used for storing and maintaining vertex data. Sp
A graphics geometry cache. The basic idea of one embodiment in accordance with the present invention is to utilize a graphics geometry cache together with a graphics pipeline. The graphics geometry cache is a relatively small cache (e.g., 128 entries) used for storing and maintaining vertex data. Specifically, the results of computations performed on vertices by the graphics pipeline (e.g., transformed vertices and attributes such as color) are cached within the graphics geometry cache. Furthermore, the cached entries are tagged by their corresponding vertex coordinates. Subsequently, when a particular vertex is specified for the graphics pipeline, a tag compare is executed through a hashing function to determine whether the graphics geometry data for that particular vertex is stored within the graphics geometry cache. If a hit occurs during the tag compare, a copy of the graphics geometry data is retrieved from the graphics geometry cache rather than having to recompute the graphics geometry data for that particular vertex. Therefore, one of the advantages of the graphics geometry cache of the present embodiment is that it saves computational resources.
대표청구항
▼
A graphics geometry cache. The basic idea of one embodiment in accordance with the present invention is to utilize a graphics geometry cache together with a graphics pipeline. The graphics geometry cache is a relatively small cache (e.g., 128 entries) used for storing and maintaining vertex data. Sp
A graphics geometry cache. The basic idea of one embodiment in accordance with the present invention is to utilize a graphics geometry cache together with a graphics pipeline. The graphics geometry cache is a relatively small cache (e.g., 128 entries) used for storing and maintaining vertex data. Specifically, the results of computations performed on vertices by the graphics pipeline (e.g., transformed vertices and attributes such as color) are cached within the graphics geometry cache. Furthermore, the cached entries are tagged by their corresponding vertex coordinates. Subsequently, when a particular vertex is specified for the graphics pipeline, a tag compare is executed through a hashing function to determine whether the graphics geometry data for that particular vertex is stored within the graphics geometry cache. If a hit occurs during the tag compare, a copy of the graphics geometry data is retrieved from the graphics geometry cache rather than having to recompute the graphics geometry data for that particular vertex. Therefore, one of the advantages of the graphics geometry cache of the present embodiment is that it saves computational resources. orary storage means to subject the image data to a predetermined coding process and, when a predetermined unit processing amount of data has been subjected to the coding process, generating process information indicating this; and a control information generating means for generating first control information used by said image input control means to control the storage, and generating second control information used by said coding means to control the coding process, in accordance with the storage information generated by said storage control means and the process information generated by said coding means. 2. An image processing apparatus as defined in claim 1, wherein said control information generating means generates, as the first control information, storage stop information indicating that the storage of the input image data should be stopped, and generates, as the second control information, coding stop information indicating that the coding process should be stopped. 3. An image processing apparatus as defined in claim 1, wherein said control information generating means generates, as the first control information, storage stop information indicating that the storage of the input image data should be stopped, and generates, as the second control information, continuous process information indicating how many times said coding means can continuously perform the coding process on the unit processing amount of image data. 4. An image processing apparatus as defined in claim 1, wherein said control information generating means comprises: a storage information counting means for counting the storage information and holding the result as a storage information count value; a process information counting means for counting the process information and holding the result of the count as a process information count value; an addition control means for outputting an addition enabling signal when the count of the storage information is performed a predetermined number of times, and outputting an addition disabling signal when the count of the process information is performed a predetermined number of times; a storage information count value change means for adding a predetermined value to the storage information count value according to the addition enabling signal or the addition disabling signal, thereby generating a storage information count value after processing; a codable unit number generating means for subtracting the process information count value from the storage information count value after processing, thereby generating a codable unit number; a first control information generating means for comparing the codable unit number with a first predetermined value and, when these values match, generating the first control information; and a second control information generating means for comparing the codable unit number with a second predetermined value and, when these values match, generating the second control information. 5. An image processing apparatus as defined in claim 1, wherein said control information generating means comprises: a storage information counting means for counting the storage information and holding the result as a storage information count value; a process information counting means for counting the process information and holding the result as a process information count value; an addition control means for outputting an addition enabling signal when the count of the storage information has been performed a predetermined number of times, and outputting an addition disabling signal when the count of the process information has been performed a predetermined number of times; a storage information count value change means for adding a predetermined value to the storage information count value according to the addition enabling signal or the addition disabling signal, thereby generating a storage information count value after processing; a codable unit number generating means for
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