초록 ▼

A spreadsheet program directly publishes a data table or chart into an HTML document. The table or chart is published to a predefined location within the HTML document and a user is enabled to readily update the published table or chart to include changes made in the spreadsheet program by republish

A spreadsheet program directly publishes a data table or chart into an HTML document. The table or chart is published to a predefined location within the HTML document and a user is enabled to readily update the published table or chart to include changes made in the spreadsheet program by republishing the data table or chart. Furthermore, the published or republished data can be imported back into the parent spreadsheet program from the HTML document without loss of functionality or formatting that it had in the parent spreadsheet program. In addition, the data may be published in a form that can be used by ActiveX web components in order to provide spreadsheet functionality from within the browser application. A unique marker tag or identification tag within the HTML document indicates where the data table or chart has been inserted.

대표청구항 ▼

A spreadsheet program directly publishes a data table or chart into an HTML document. The table or chart is published to a predefined location within the HTML document and a user is enabled to readily update the published table or chart to include changes made in the spreadsheet program by republish

A spreadsheet program directly publishes a data table or chart into an HTML document. The table or chart is published to a predefined location within the HTML document and a user is enabled to readily update the published table or chart to include changes made in the spreadsheet program by republishing the data table or chart. Furthermore, the published or republished data can be imported back into the parent spreadsheet program from the HTML document without loss of functionality or formatting that it had in the parent spreadsheet program. In addition, the data may be published in a form that can be used by ActiveX web components in order to provide spreadsheet functionality from within the browser application. A unique marker tag or identification tag within the HTML document indicates where the data table or chart has been inserted. that control analog switches. 6. A method as defined in claim 5, including a first update signal for controlling update latches that control analog switches and a second update signal for controlling all other update latches, said updating all update latches including activating said first and said second update signals in said UpdateDR state of said controller and said updating only update latches including activating said second update signal and de-activating said second update signal in said UpdateDR state of said controller. 7. A method for sequentially accessing circuit nodes in an IEEE 1149.4 compatible mixed-signal circuit having analog busses for accessing said signal nodes, a test access port controller, an analog boundary module associated with each said circuit node, each module having shift register elements, each shift register element having an associated update latch, and analog switches for selectively accessing said busses, a plurality of said shift register elements and associated update latches controlling said analog switches, said method comprising: accessing a first of said circuit nodes including: serially loading logic values into said boundary modules, said logic values including an analog switch enabling logic value for enabling an analog switch associated with said first of said circuit nodes; activating an update signal to update the latch output of update latches associated boundary modules so as to enable said analog switch associated with said first of said circuit nodes; monitoring or driving said first signal node via said analog bus; and for each additional circuit node to be accessed: without performing a capture of the signal node logic values and without enabling other analog switches, serially loading additional logic values into said boundary modules until said analog switch enabling logic value is shifted to the next boundary module that controls a next analog switch associated with a next signal node in sequence to be accessed; activating an update signal to disable said first analog switch and enable said next analog switch; and monitoring or driving the second signal node via the analog bus. 8. A method as defined in claim 7, said serially loading logic values including loading logic 0's to disable all signal node drivers and analog switches, except for a single logic 1 for a boundary module that controls an analog switch associated with said first of said circuit nodes; and said serially loading additional logic values comprising serially loading logic 0's. 9. A method as defined in claim 7, said serially loading logic values including loading logic 0's for disabling all signal node drivers and analog switches, except for two logic 1's for boundary modules which control two analog switches associated with said first of said circuit nodes; and said serially loading additional logic values comprising serially loading logic 0's. 10. A method as defined in claim 7, further including, following said serial loading, loading a logic value into an additional latch associated with each of predetermined boundary modules for preventing updating of said update additional latches; and said activating an update signal to cause the first analog switch to be disabled including, for each boundary module whose updating has not been prevented by said additional latch, updating update latch output values by a transition of the first update signal, to disable said first analog switch and enable said next analog switch. 11. A method as defined in claim 7, said activating an update signal to update the latch output including applying a first update signal to each said update latch, and said activating an update signal to cause the first analog switch to be disabled including applying a second update signal to update latches which control said analog switches. 12. A method as defined in claim 7, further including: generating a first update signal input for each boundary module tha t controls digital drivers that drive the signal nodes; generating a second update signal for each boundary module that controls analog switches; and applying a programmable register bit for controlling whether, during an UpdateDR state of said TAP controller, the first and second update signals are activated in unison or only the second update signal is activated. 13. A method as defined in claim 7, said serially loading including loading logic values that cause signal node drivers to drive signals nodes to predetermined logic states. 14. A method for sequentially accessing circuit nodes in an IEEE 1149.4 compatible mixed-signal circuit having analog busses for accessing said signal nodes, a test access port controller, an analog boundary module associated with each said circuit node, each module having shift register elements, associated update latches, a pair of analog switches for selectively accessing said busses and shift register elements for controlling said analog switches, said controller having a plurality of states including a ShiftDR for loading logic values into said boundary modules, CaptureDR for capturing the signal at the input of a boundary scan shift register element, and UpdateDR for updating latches associated with said shift register element, said method comprising: accessing a first of said circuit nodes including: configuring said controller in said ShiftDR sate and serially loading logic values into said boundary modules, said logic values including an analog switch enabling logic value for enabling an analog switch associated with said first of said circuit nodes; configuring said controller in said UpdateDR state to update the latch output of update latches associated with said boundary modules so as to enable said analog switch associated with said first of said circuit nodes and disable all other switches; monitoring or driving said first signal node via one or both of said analog buses; for each additional circuit node to be accessed: configuring said controller in said ShiftDR state including: disabling the clock input of said update latch to suppress capture as said controller passes through said CaptureDR state and serially loading additional logic values into said boundary modules until said analog switch enabling logic value is shifted to the next boundary module in sequence that controls a next analog switch connected to a next signal node in sequence to be accessed; configuring said controller in said UpdateDR state to update the latch output of update latches associated with said analog switches to activate said switch enabling logic value in said next analog switch to be enabled; and monitoring or driving the second signal node via the analog bus. 15. A method as defined in claim 14, said suppressing capture including disabling the clock signal applied to update latches associated with said boundary modules. 16. A method for sequentially accessing circuit nodes in a circuit having IEEE 1149.4 compatible mixed-signal integrated circuits each having a test access port controller having a plurality of states including ShiftDR, UpdateDR and CaptureDR, a boundary scan register having a boundary modules associated with each said circuit node, analog busses for accessing said circuit nodes and connecting said controller and each said boundary module, said boundary modules including an analog boundary module having analog switches for selectively accessing said busses, shift register elements and associated update latches for controlling said analog switches, said method comprising: initializing said boundary modules with logic values including an analog switch enabling logic value for enabling an analog switch associated with a first circuit node and enabling said associated analog switch; monitoring or driving said first signal node via said analog busses; suppressing capture operation in each said boundary modules; and for each additional circuit node to be acc