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A method and system of testing and verifying computer code in a multi-threaded environment. The method includes testing a first piece of computer code that is an implementation of a specification against a second piece of computer code that is a different implementation of the specification. Corresp

A method and system of testing and verifying computer code in a multi-threaded environment. The method includes testing a first piece of computer code that is an implementation of a specification against a second piece of computer code that is a different implementation of the specification. Corresponding synchronization points in the first and second pieces of code are defined and the first piece of code is executed to the first synchronization point of the first piece of code. A state message is generated and sent to the second piece of code. The second piece of code is executed to the first synchronization point of the second piece of code and then a state after message is generated and compared to the state before message. The synchronization points are generally selected from a group including conditional transfers of control, Method calls, Method returns, and backward transfers of control.

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A method and system of testing and verifying computer code in a multi-threaded environment. The method includes testing a first piece of computer code that is an implementation of a specification against a second piece of computer code that is a different implementation of the specification. Corresp

A method and system of testing and verifying computer code in a multi-threaded environment. The method includes testing a first piece of computer code that is an implementation of a specification against a second piece of computer code that is a different implementation of the specification. Corresponding synchronization points in the first and second pieces of code are defined and the first piece of code is executed to the first synchronization point of the first piece of code. A state message is generated and sent to the second piece of code. The second piece of code is executed to the first synchronization point of the second piece of code and then a state after message is generated and compared to the state before message. The synchronization points are generally selected from a group including conditional transfers of control, Method calls, Method returns, and backward transfers of control. the resulting data being written to a data transfer register. 11. An integrated circuit as claimed in claim 10, wherein said data transfer register is one of said circuit elements, and the scan chain register is arranged to store the scan chain specifying value identifying the test scan chain coupled to the data transfer register, that test scan chain incorporating a shift register for shifting data into and out of said data transfer register. 12. An integrated circuit as claimed in claim 11, wherein once data has been written to the data transfer register, the decoder is responsive to a third scan chain controller instruction to cause the scan chain selector to be coupled to the serial interface to enable the data in the data transfer register to be stored into the shift register of the test scan chain coupled to the data transfer register and then output over the serial interface. 13. An integrated circuit as claimed in claim 9, wherein one of said circuit elements is a data transfer register, and the scan chain register is arranged to store the scan chain specifying value identifying the test scan chain coupled to the data transfer register, that test scan chain incorporating a shift register for shifting data into and out of said data transfer register. 14. An integrated circuit as claimed in claim 13, wherein data is first stored in the data transfer register using the second scan chain controller instruction, and then the first scan chain controller instruction is used to shift instruction data into the shift register, from where it is written into the instruction transfer register. 15. An integrated circuit as claimed in claim 14, wherein the microprocessor is caused to execute the instruction specified by the instruction data, this causing the data in the data transfer register to be transferred to a location accessible by the microprocessor. 16. A method of operating an integrated circuit comprising a plurality of circuit elements, and a plurality of serial test scan chains each coupled to a different one of said circuit elements, the method comprising the steps of: responsive to a specified scan chain specifying value, selecting a corresponding one of said plurality of test scan chains; employing a decoder to decode scan chain controller instructions received at a serial interface of the integrated circuit; the decoder being responsive to a first scan chain controller instruction to specify a predetermined scan chain specifying value and a second scan chain controller instruction for decoding by the decoder. 17. A computer program product carrying a computer program for controlling an integrated circuit comprising a plurality of circuit elements, and a plurality of serial test scan chains each coupled to a different one of said circuit elements, the computer program causing the integrated circuit to pet-form the steps of: responsive to a specified scan chain specifying value, selecting a corresponding one of said plurality of