초록

Natural gas liquefaction system having an optimum configuration of mechanical drivers and compressors. A heat recovery system can be employed with the liquefaction system to enhance thermal efficiency. A unique start-up system can also be employed.

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Natural gas liquefaction system having an optimum configuration of mechanical drivers and compressors. A heat recovery system can be employed with the liquefaction system to enhance thermal efficiency. A unique start-up system can also be employed. ense amplifier activating signal in response to an

Natural gas liquefaction system having an optimum configuration of mechanical drivers and compressors. A heat recovery system can be employed with the liquefaction system to enhance thermal efficiency. A unique start-up system can also be employed. ense amplifier activating signal in response to an output signal of said potential detecting circuits; and a sense amplifier activated in response to the sense amplifier activating signal, to amplify data of a selected normal memory cell. 10. The semiconductor memory device according to claim 9, wherein said sense amplifier is coupled through a column select gate to a normal bit line connected to the selected normal memory cell, and amplifies differentially a potential on the normal bit line connected to the selected normal memory cell when activated. 11. The semiconductor memory device according to claim 9, wherein the dummy cell columns are arranged at an end of a memory cell array including the normal memory cells; and said semiconductor memory device further comprises a plurality of columns of edge cells arranged in rows and columns in said memory cell array, adjacent to the dummy cell columns, respectively, the edge cells each having a same configuration as the normal memory cell. 12. The semiconductor memory device according to claim 11, wherein an internal node of each edge cell is fixed to a ground voltage level. 13. The semiconductor memory device according to claim 11, further comprising: edge bit lines, arranged corresponding to the columns of said edge cells, each connected to the edge cells in a corresponding column and fixed to a ground voltage level. 14. The semiconductor memory device according to claim 11, wherein a column of the dummy cell columns is arranged between a column of said edge cells and a column of the normal memory cells. 15. The semiconductor memory device according to claim 1, wherein the normal memory cells are arranged in memory arrays placed on opposite sides of a row decode circuit producing a row select signal, and the plurality of dummy cells are arranged at a side of each of said memory cell arrays near said row decode circuit. 16. The semiconductor memory device according to claim 1, wherein each of the plurality of dummy cells includes an access transistor rendered conductive in response to a signal on a corresponding word line, and gates of the access transistors of a predetermined number of dummy cells arranged in a column direction of the plurality of dummy cells are interconnected. 17. The semiconductor memory device according to claim 9, wherein said potential detecting circuits each include: a gate circuit coupled to a corresponding dummy bit line through a high input impedance and activated to amplify and output a potential on the corresponding dummy bit line in response to an operation mode instructing signal. 18. The semiconductor memory device according to claim 17, wherein said gate circuit includes: a CMOS inverter for receiving a potential on the corresponding dummy bit line, and a latch gate responsive to activation of said operation mode instructing signal, for driving the potential on the corresponding dummy bit line to a predetermined voltage level in accordance with an output signal of said CMOS inverter. 19. The semiconductor memory device according to claim 17, wherein said gate circuits each include an insulated gate field effect transistor having a gate coupled to the corresponding dummy bit line for driving an internal node to a first potential level in response to the potential on the corresponding dummy bit line, said internal node being arranged commonly to said gate circuits; and said sense amplifier activating circuit includes; a precharge transistor for precharging said internal node to a first voltage level, a latch amplifier for activating and latching the sense amplifier activating signal in response to the potential on said internal node. 20. The semiconductor memory device according to claim 17, wherein said sense amplifier activating circuit activates said sense amplifier activating signal when at least one of said potential detecting circuits provides an output signal at a first logical le vel. s to control switching operations of the switching elements of said inverter main circuit. 2. A power inverter as set forth in claim 1, wherein said voltage command converter determines one of the first voltage commands selected as each of the A-phase voltage command and the B-phase voltage command as a function of a phase difference between the first voltage command and the current outputted to the polyphase load. 3. A power inverter as set forth in claim 1, wherein when one of the second voltage commands into which the B-phase voltage command is converted in the second conversion cycle lies out of a range of the maximum level to the minimum level, one of the second voltage commands into which the B-phase voltage command is converted in the first conversion cycle being corrected to a value reversed in polarity, the second voltage command into which the B-phase voltage command is converted in the second conversion cycle being corrected to a value that is equal to an excess of the second voltage command over the range of the maximum to minimum level. 4. A power inverter as set forth in claim 1, wherein the number of phases of the polyphase load is three. 5. A power inverter as set forth in claim 1, wherein the polyphase load is an AC motor. 6. A power inverter outputting power to a polyphase load comprising: an inverter main circuit working to apply phase voltages to the polyphase load through switching elements; a voltage command outputting circuit outputting first voltage commands for respective phases, each of the first voltage commands varying between a maximum and a minimum level; a voltage command converter converting the first voltage commands outputted by said voltage command outputting circuit into second voltage commands in a first and a second conversion cycle which are provided alternately, said voltage command converter converting two of the first voltage commands into the second voltage commands that are identical with one of the maximum and minimum levels in the first conversion cycle and also converting one of the two of the first voltage commands into the second voltage command that is identical with one of the maximum and minimum levels in the second conversion cycle, assuming that one of the two of the first voltage commands which is converted into the second voltage command that is equal to the one of the maximum and minimum levels only in the first conversion cycle is defined as a third voltage command, when the second voltage command into which the third voltage command is converted in the second conversion cycle lies out of a range of the maximum level to the minimum level, the second voltage command into which the third voltage command being converted in the first conversion cycle being corrected to a value reversed in polarity, the second voltage command into which the third voltage command being converted in the second conversion cycle being corrected to a value that is equal to an excess of the second voltage command over the range of the maximum to minimum level; and a switching control signal outputting circuit working to pulse-width modulate a carrier wave as functions of the respective second voltage commands to output switching control signals for the respective phases to control switching operations of the switching elements of said inverter main circuit. 7. A power inverter as set forth in claim 6, wherein if the other of the two of the first voltage commands as being converted into the second voltage commands that is equal to the one of the maximum and minimum level both in the first conversion cycle and the second conversion cycle is defined as a fourth voltage command, said voltage command converter changes one of the first voltage commands selected as each of the third voltage command and the fourth voltage command as a function of a given parameter. 8. A power inverter as set forth in claim 6, wherein the number of phases of the polyphase load is three. 9. A power inverter as set forth in claim 6, wherein the polyphase load is an AC motor. 10. A method of outputting power to a polyphase load from an inverter main circuit comprising the steps of: outputting first voltage commands for respective phases each of which varies between a maximum and a minimum level; converting the first voltage commands outputted by said voltage command outputting circuit into second voltage commands in a first and a second conversion cycle which are provided alternately, in the first conversion cycle, two of the first voltage commands being converted into the second voltage commands that are equal to one of the maximum and minimum levels, in the second conversion cycle, one of the two of the first voltage commands being converted into the second voltage command that is equal to one of the maximum and minimum levels, if the one of the first voltage commands as being converted into the second voltage command that is equal to the one of the maximum and minimum levels both in the first and second conversion cycles is defined as an A-phase voltage command, the A-phase voltage command being selected as one of two of the first voltage commands showing the maximum and minimum levels within the first and second conversion cycles which is greater in absolute value of a corresponding current outputted to the polyphase load, if the other of the two of the first voltage commands as being converted into the second voltage commands that is equal to the one of the maximum and minimum level only in the first conversion cycle is defined as a B-phase voltage command, the B-phase voltage command being selected as one of the first voltage commands which is greater in absolute value of a corresponding current outputted to the polyphase load next to the A-phase voltage command; and pulse-width modulating a carrier wave as functions of the respective second voltage commands to output switching control signals for the respective phases to control switching operations of switching elements of the inverter main circuit for driving the polyphse load. 11. A method as set forth in claim 10, wherein one of the first voltage commands selected as each of the A-phase voltage command and the B-phase voltage command being determined as a function of a phase difference between the first voltage command and the current outputted to the polyphase load. 12. A method as set forth in claim 10, wherein when one of the second voltage commands into which the B-phase voltage command is converted in the second conversion cycle lies out of a range of the maximum level to the minimum level, one of the second voltage commands into which the B-phase voltage command is converted in the first conversion cycle being corrected to a value reversed in polarity, the second voltage command into which the B-phase voltage command is converted in the second conversion cycle being corrected to a value that is equal to an excess of the second voltage command over the range of the maximum to minimum level. 13. A method as set forth in claim 10, wherein the number of phases of the polyphase load is three. 14. A method as set forth in claim 10, wherein the polyphase load is an AC motor. 15. A method of outputting power to a polyphase load from an inverter main circuit comprising the steps of: outputting first voltage commands for respective phases each of which varies between a maximum and a minimum level; converting the first voltage commands outputted by said voltage command outputting circuit into second voltage commands in a first and a second conversion cycle which are provided alternately, in the first conversion cycle, two of the first voltage commands being converted into the second voltage commands that are identical with one of the maximum and minimum levels, in the second conversion cycle, one of the two of the first voltage commands being converted into the second voltage command that is identical with one of the maximum and minimum levels, assuming that one of the t wo of the first voltage commands which is converted into the second voltage command that is equal to the one of the maximum and minimum levels only in the first conversion cycle is defined as a third voltage command, when the second voltage command into which the third voltage command is converted in the second conversion cycle lies out of a range of the maximum level to the minimum level, the second voltage command into which the third voltage command being converted in the first conversion cycle being corrected to a value reversed in polarity, the second voltage command into which the third voltage command being converted in the second conversion cycle being corrected to a value that is equal to an excess of the second voltage command over the range of the maximum to minimum level; and pulse-width modulating a carrier wave as functions of the respective second voltage commands to output switching control signals for the respective phases to control switching operations of switching elements of said inverter main circuit for driving the polyphase load. 16. A method as set forth in claim 15, wherein if the other of the two of the first voltage commands as being converted into the second voltage commands that is equal to the one of the maximum and minimum level both in the first conversion cycle and the second conversion cycle is defined as a fourth voltage command, one of the first voltage commands selected as each of the third voltage command and the fourth voltage command being changed as a function of a given parameter. 17. A method as set forth in claim 15, wherein the number of phases of the polyphase load is three. 18. A method as set forth in claim 15, wherein the polyphase load is an AC motor.