Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
C25D-005/02
C25D-007/12
출원번호
US-0656843
(2000-09-07)
발명자
/ 주소
Chen, Chih-Shun
Yuan, Po-Hao
Chiu, Shih-Kuang
Chien, Feng-Lung
Yang, Ke-Chuan
출원인 / 주소
Siliconware Precision Industries Co., Ltd.
대리인 / 주소
Corless, Peter F.Jensen, Steven M.Edwards & Angell, LLP
인용정보
피인용 횟수 :
7인용 특허 :
12
초록▼
A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a prede
A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a predefined cutting line and each of which is formed with a plurality of aluminum or copper based bond pads, and is characterized in the provision of a plating bus over and along the cutting line and connected to each bond pad. By means of this plating bus, the required UBM (Under Bump Metallization) fabrication and solder-bump fabrication can be both carried out through plating. Since plating process is considerably lower in cost than sputtering process and etching process, the proposed flip-chip bumping method can be more cost-effective to implement than prior art.
대표청구항▼
A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a prede
A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a predefined cutting line and each of which is formed with a plurality of aluminum or copper based bond pads, and is characterized in the provision of a plating bus over and along the cutting line and connected to each bond pad. By means of this plating bus, the required UBM (Under Bump Metallization) fabrication and solder-bump fabrication can be both carried out through plating. Since plating process is considerably lower in cost than sputtering process and etching process, the proposed flip-chip bumping method can be more cost-effective to implement than prior art. US-5656111, 19970800, Dilnik et al.; US-5665396, 19970900, Ulman; US-5692939, 19971200, DesMarais; US-5725821, 19980300, Gannon et al.; US-5807365, 19980900, Luceri; US-5833679, 19981100, Wada, 604/384; US-5849000, 19981200, Anjur et al.; US-5858512, 19990100, Dit Picard et al.; US-5871763, 19990200, Luu et al.; US-5906879, 19990500, Huntoon et al.; US-5916203, 19990600, Brandon et al.; US-5916678, 19990600, Jackson et al.; US-5938995, 19990800, Koltisko, Jr. et al.; US-5948710, 19990900, Pomplun et al.; US-5958275, 19990900, Joines et al.; US-5962112, 19991000, Haynes et al.; US-5968430, 19991000, Naito et al.; US-5990377, 19991100, Chen et al.; US-6000102, 19991200, Lychou; US-6001300, 19991200, Buckley; US-6020580, 20000200, Lewis et al.; US-6080691, 20000600, Lindsay et al.; US-6085437, 20000700, Stipp; US-6098249, 20000800, Toney et al.; US-6120783, 20000900, Roe et al.; US-6171682, 20010100, Raidel et al.; US-6191340, 20010200, Carlucci et al.; US-6264791, 20010700, Sun et al.; US-6326525, 20011200, Hamajim et al.; US-6486379, 20021100, Chen et al., 604/378; US-20020032421, 20020300, Scott et al., 604/367
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