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Semiconductor device having a thin film transistor and manufacturing method thereof 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/01
출원번호 US-0709071 (1996-09-06)
우선권정보 JP-0107294 (1996-04-26)
발명자 / 주소
  • Maegawa, Shigeto
  • Ipposhi, Takashi
  • Iwamatsu, Toshiaki
출원인 / 주소
  • Mitsubishi Denki Kabushiki Kaisha
대리인 / 주소
    McDermott, Will & Emery
인용정보 피인용 횟수 : 64  인용 특허 : 11

초록

A semiconductor layer has one end placed on top of a first conductive layer and in contact with the first conductive layer, and the other end placed on top of a second conductive layer and in contact with the second conductive layer. At the central portion, the semiconductor layer faces a gate elect

대표청구항

A semiconductor layer has one end placed on top of a first conductive layer and in contact with the first conductive layer, and the other end placed on top of a second conductive layer and in contact with the second conductive layer. At the central portion, the semiconductor layer faces a gate elect

이 특허에 인용된 특허 (11)

  1. Ngaoaram Sukhum (Singapore SGX), Dual ion implantation process for gate oxide improvement.
  2. Vinal Albert W. (Cary NC) Dennen Michael W. (Raleigh NC), Field effect transistor having polycrystalline silicon gate junction.
  3. Yamazaki Shunpei (Tokyo JPX), Gate insulated field effect transistors and method of manufacturing the same.
  4. Yamazaki Shunpei (Tokyo JPX), Insulated gate field effect transistor.
  5. Wu Chung P. (Mercer NJ) Schnable George L. (Lansdale PA), Ion-implantation of phosphorus, arsenic or boron by pre-amorphizing with fluorine ions.
  6. Ishida Mamoru (Yokohama JPX), MIS semiconductor device with polysilicon gate electrode.
  7. Shirasaki Masahiro (Kawasaki JPX), MIS transistor structure for increasing conductance between source and drain regions.
  8. Lifshitz Nadia (Bridgewater NJ) Luryi Serge (Bridgewater NJ), Metal oxide semiconductor transistors having a polysilicon gate electrode with nonuniform doping in source-drain directi.
  9. Haddad Sameer S. (San Jose CA) Liang Mong-Song (Milpitas CA), Method of improving silicon dioxide.
  10. Yoh, Kanji; Yamashiro, Osamu; Meguro, Satoshi, Method of manufacturing a reference voltage generator device.
  11. Lee Kuo-Hua (Wescosville PA) Liu Chun-Ting (Wescosville PA), Thin film transistor having increased effective channel width.

이 특허를 인용한 특허 (64)

  1. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  2. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  3. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  4. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  5. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  6. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  15. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  16. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  17. Juengling, Werner, Masking process for simultaneously patterning separate regions.
  18. Juengling, Werner, Memory device comprising an array portion and a logic portion.
  19. Juengling, Werner, Memory device comprising an array portion and a logic portion.
  20. Datta,Suman; Doyle,Brian S.; Chau,Robert S.; Kavalieros,Jack; Zheng,Bo; Hareland,Scott A., Method and apparatus for improving stability of a 6T CMOS SRAM cell.
  21. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  22. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  23. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  24. Yu,Bin; Ahmed,Shibly S.; An,Judy Xilin; Dakshina Murthy,Srikanteswara; Krivokapic,Zoran; Wang,Haihong, Method of manufacturing a semiconductor device having a fin structure.
  25. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  26. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  27. Juengling, Werner; Lane, Richard, Methods of forming an integrated circuit with self-aligned trench formation.
  28. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  29. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  30. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  31. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  32. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  33. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  34. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  35. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  36. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  37. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  38. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  39. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  40. Brask,Justin K.; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  41. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  42. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  43. Juengling, Werner; Lane, Richard, Self-aligned semiconductor trench structures.
  44. Werner, Juengling; Lane, Richard, Self-aligned semiconductor trench structures.
  45. Juengling, Werner; Lane, Richard, Self-aligned trench formation.
  46. Muraoka,Kouichi; Kurihara,Kazuaki, Semiconductor device and method of manufacturing the same.
  47. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  48. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  49. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  50. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  51. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  52. Yamazaki,Shunpei; Miyanaga,Akiharu; Koyama,Jun; Fukunaga,Takeshi, Static random access memory using thin film transistors.
  53. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  54. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  55. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  56. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  57. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  58. Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Thin film semiconductor device and its manufacturing method.
  59. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  60. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  61. Juengling, Werner, Vertical gated access transistor.
  62. Juengling, Werner, Vertical gated access transistor.
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  64. Juengling,Werner, Vertical gated access transistor.
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