초록 ▼

A mattress support element comprises a fluid filled bladder and a fluid container substantially surrounded by the bladder. The fluid container is in constant fluid communication with ambient fluid outside the bladder. The fluid container is configured to deform from its original shape when an extern

A mattress support element comprises a fluid filled bladder and a fluid container substantially surrounded by the bladder. The fluid container is in constant fluid communication with ambient fluid outside the bladder. The fluid container is configured to deform from its original shape when an external force is applied to the bladder and to reform to its original shape upon removal of the external force from the bladder.

대표청구항 ▼

A mattress support element comprises a fluid filled bladder and a fluid container substantially surrounded by the bladder. The fluid container is in constant fluid communication with ambient fluid outside the bladder. The fluid container is configured to deform from its original shape when an extern

A mattress support element comprises a fluid filled bladder and a fluid container substantially surrounded by the bladder. The fluid container is in constant fluid communication with ambient fluid outside the bladder. The fluid container is configured to deform from its original shape when an external force is applied to the bladder and to reform to its original shape upon removal of the external force from the bladder. from the common attributes associated with the remaining subsets. 8. The method as recited in claim 1 wherein associating subsections of said grid further includes forming said plurality of tiles so that multiple subsets of said plurality of data points associated with one of said plurality of tiles have common attributes, with a number of said subsets being a function of a wire pitch and a periodicity of said plurality of data points. 9. A method for storing, in a computer readable medium, a data structure containing wire routing information of an integrated circuit, said method comprising: mapping said integrated circuit into memory locations of said medium as a wiring plane having a plurality of data points arranged in a grid with a periodicity so that a distance between adjacent data points is less than a minimum wire pitch, with each of said plurality of data points having state information associated therewith, said state information including a plurality of attributes; and associating subsections of said grid with sets of said memory locations in said computer readable medium to form a plurality of tiles having a width, wt,approximately equal to said minimum wiring pitch so that a sub-portion of said data points associated with one of said plurality of tiles have common attributes. 10. The method as recited in claim 9 wherein said attributes are selected from a set consisting of status, location, net identifies, shape definition, shape class and conducting path cost and said common attributes are selected from a set consisting of shape definition, shape class and net identifier. 11. The method as recited in claim 10 wherein associating subsections of said grid further includes forming said plurality of tiles so that multiple subsets of said plurality of data points associated with one of said plurality of tiles have common attributes, with a number of said subsets being a function of a wire pitch and a periodicity of said plurality of data points. 12. The method as recited in claim 11 wherein the common attributes associated with one of said subsets differing from the common attributes associated with the remaining subsets. 13. The method as recited in claim 12 wherein mapping said integrated circuit further includes mapping said integrated circuit as a plurality of wiring planes, each of which has said plurality of data points arranged in said grid. on et al., 707/103.Y; US-6567818, 20030500, Frey et al., 707/103.R; US-6567905, 20030500, Otis, 711/170; US-6629153, 20030900, Gupta et al., 709/316