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Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • H01L-021/44
출원번호 US-0809670 (2001-03-15)
발명자 / 주소
  • Ahn, Kie Y.
  • Forbes, Leonard
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Whyte Hirschboeck Dudek SC
인용정보 피인용 횟수 : 23  인용 특허 : 24

초록

A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and m

대표청구항

A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and m

이 특허에 인용된 특허 (24)

  1. Farrar Paul A. ; Givens John H., Alloy for enhanced filling of high aspect ratio dual damascene structures.
  2. Lu Toh-Ming (Latham NY) Mei Shao-Ning (Wappingers Falls NY), Deposition of metals on stepped surfaces.
  3. Moradi Behnam ; Raina Kanwal K. ; Westphal Michael J., Field emission display cathode assembly government rights.
  4. Batra Shubneesh ; Sandhu Gurtej, Low temperature reflow method for filling high aspect ratio contacts.
  5. Forbes Leonard ; Noble Wendell P., Memory address decode array with vertical transistors.
  6. Grabarz Henry J. (Huntington CT) Grill Alfred (White Plains NY) Holber William M. (New York NY) Logan Joseph S. (Poughkeepsie NY) Yeh James T. C. (Katonah NY), Method and apparatus for filing high aspect patterns with metal.
  7. Somekh Sasson (Los Altos Hills CA) Nulman Jaim (Palo Alto CA) Chang Mei (Cupertino CA), Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer.
  8. Ahn Kie Y., Method of fabricating integrated circuit wiring with low RC time delay.
  9. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Method of forming a smooth copper seed layer for a copper damascene structure.
  10. Forbes Leonard ; Farrar Paul A. ; Ahn Kie Y., Methods and structures for gold interconnections in integrated circuits.
  11. Ahn Kie Y. ; Forbes Leonard, Methods for making copper and other metal interconnections in integrated circuits.
  12. Ahn Kie Y. ; Forbes Leonard, Multichip module with built in repeaters and method.
  13. Kim Edwin ; Nam Michael ; Cha Chris ; Yao Gongda ; Lee Sophia ; Dorleans Fernand ; Kohara Gene Y. ; Fu Jianming, Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers.
  14. Takamatsu Toshiyuki,JPX ; Fujimura Shuzo,JPX, Plasma surface treatment method and resulting device.
  15. Cathey ; Jr. David A. (Boise ID), Process for fabricating conductors used for integrated circuit connections and the like.
  16. Jain Ajay, Process for forming a semiconductor device.
  17. Kaoru Mikagi JP, Semiconductor device and method for making the same.
  18. Mikagi Kaoru,JPX, Semiconductor device and method for making the same.
  19. Takagi Hideo,JPX ; Uji Shigetaka,JPX ; Hirao Shyoji,JPX, Semiconductor device manufacturing method.
  20. Hamamoto Takeshi (Kawasaki JPX) Horiguchi Fumio (Tokyo JPX) Hieda Katsuhiko (Yokohama JPX), Semiconductor memory with pad electrode and bit line under stacked capacitor.
  21. Richard J. Huang ; Guarionex Morales ; Simon Chan, Surface treatment of low-K SiOF to prevent metal interaction.
  22. Huang Richard J. ; Morales Guarionex ; Chan Simon, Surface treatment of low-k SiOF to prevent metal interaction.
  23. Forbes Leonard ; Ahn Kie Y., Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits.
  24. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (23)

  1. Brown, Karl M.; Pipitone, John; Mehta, Vineet; Hofmann, Ralf, Apparatus for plasma-enhanced physical vapor deposition of copper with RF source power applied through the workpiece with a lighter-than-copper carrier gas.
  2. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  3. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  4. Ahn, Kie Y; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  5. Ahn,Kie Y; Forbes,Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  6. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using enhanced reflow.
  7. Fortin,Vincent; Tsai,Kuei Chang, Cobalt silicide fabrication using protective titanium.
  8. Shih, Chien Hsueh; Tsai, Minghsing; Su, Hung Wen; Shue, Shau Lin, Copper interconnection with conductive polymer layer and method of forming the same.
  9. Avanzino, Steven C.; Wang, Pin-Chin Connie; Ngo, Minh Van, Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers.
  10. Gyun,Ahn Heui, Isolation methods in semiconductor devices.
  11. Botman, Aurelien Philippe Jean Maclou; Toth, Milos; Randolph, Steven; Narum, David H., Localized, in-vacuum modification of small structures.
  12. Narum, David H.; Toth, Milos; Randolph, Steven; Botman, Aurelien Philippe Jean Maclou, Localized, in-vacuum modification of small structures.
  13. Brown, Karl M.; Pipitone, John; Mehta, Vineet, Method for plasma-enhanced physical vapor deposition of copper with RF source power applied to the target.
  14. Brown, Karl M.; Pipitone, John; Mehta, Vineet, Method of performing physical vapor deposition with RF plasma source power applied to the target using a magnetron.
  15. Brown, Karl M.; Pipitone, John; Mehta, Vineet, Physical vapor deposition plasma reactor with RF source power applied to the target and having a magnetron.
  16. Brown, Karl M.; Sherstinksy, Semyon; Mehta, Vineet H.; Wang, Wei W.; Pipitone, John A.; Ahmann, Kurt J.; Valverde, Jr., Armando, Physical vapor deposition plasma reactor with arcing suppression.
  17. Kawano, Shuichi; Tsunoda, Koichi, Printed wiring board and method for manufacturing the same.
  18. Su, Hung-Wen; Chou, Shih-Wei; Tsai, Ming-Hsing, Semiconductor device.
  19. Su, Hung-Wen; Chou, Shih-Wei; Tsai, Ming-Hsing, Semiconductor device and method for forming the same.
  20. Su, Hung-Wen; Chou, Shih-Wei; Tsai, Ming-Hsing, Semiconductor device and method for forming the same.
  21. Clevenger, Lawrence A.; Quon, Roger A.; Spooner, Terry A.; Wang, Wei; Yang, Chih-Chao, Surface nitridation in metal interconnects.
  22. Clevenger, Lawrence A.; Quon, Roger A.; Spooner, Terry A.; Wang, Wei; Yang, Chih-Chao, Surface nitridation in metal interconnects.
  23. Gu, George Y.; Bassom, Neil J.; Gannon, Thomas J.; Liu, Kun, System for modifying small structures.
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