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Interconnect structures and a method of electroless introduction of interconnect structures 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0290776 (2002-11-07)
발명자 / 주소
  • Dubin, Valery M.
  • Thomas, Christopher D.
  • McGregor, Paul
  • Datta, Madhav
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 27  인용 특허 : 18

초록

An apparatus including a substrate comprising a device having contact point; a dielectric layer overlying the device with an opening to the contact point; and an interconnect structure disposed in the opening including an interconnect material and a different conductive shunt material.

대표청구항

1. An apparatus comprising: a substrate comprising a device having contact point; a dielectric layer overlying the device with an opening to the contact point; and an interconnect structure disposed in the opening comprising an interconnect material and a different conductive shunt material; w

이 특허에 인용된 특허 (18)

  1. Shacham Yosef Y. (Ithaca NY) Bielski Roman (Ithaca NY), Alkaline free electroless deposition.
  2. Hsiung Chiung-Sheng,TWX ; Hsieh Wen-Yi,TWX ; Lur Water,TWX, Copper damascene technology for ultra large scale integration circuits.
  3. Edelstein Daniel C. ; Dalton Timothy J. ; Gaudiello John G. ; Krishnan Mahadevaiyer ; Malhotra Sandra G. ; McGlashan-Powell Maurice ; O'Sullivan Eugene J. ; Sambucetti Carlos J., Dual etch stop/diffusion barrier for damascene interconnects.
  4. Dubin Valery M. ; Shacham-Diamand Yosef ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications.
  5. Kumasaka Osamu (Yamanashi JPX) Yamaoka Nobuki (Yamanashi JPX), Electroless plating method and apparatus.
  6. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
  7. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
  8. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  9. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  10. Steven C. Avanzino ; Kai Yang ; Sergey Lopatin ; Todd P. Lukanc, Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film.
  11. Daniel C. Edelstein ; Timothy J. Dalton ; John G. Gaudiello ; Mahadevaiyer Krishnan ; Sandra G. Malhotra ; Maurice McGlashan-Powell ; Eugene J. O'Sullivan ; Carlos J. Sambucetti, Method of forming barrier layers for damascene interconnects.
  12. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  13. Gilton Terry L. (Boise ID) Tuttle Mark E. (Boise ID) Cathey David A (Boise ID), Process for metallizing integrated circuits with electrolytically-deposited copper.
  14. Hussein Makarem A., Process to manufacture continuous metal interconnects.
  15. Baum Thomas H. (San Jose CA) Houle Frances A. (Fremont CA) Jones Carol R. (San Jose CA) Kovac Caroline A. (Ridgefield CT), Selective deposition of copper.
  16. Hoshino Kazuhiro (Tokyo JPX), Semiconductor device using copper metallization.
  17. Uzoh Cyprian E., Triple damascence tungsten-copper interconnect structure.
  18. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (27)

  1. Dubin, Valery M.; Moon, Peter K., Apparatus for an improved air gap interconnect structure.
  2. Ivanov, Igor C., Barrier layer configurations and methods for processing microelectronic topographies having barrier layers.
  3. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  4. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  5. Dory,Thomas S.; Wong,Kenneth N., Deep via seed repair using electroless plating chemistry.
  6. Lin, Yaojian; Cao, Haijing; Looi, Wan Lay; Lim, Eng Seng, Integrated circuit system with metal-insulator-metal circuit element.
  7. Dubin,Valery M., Integrated circuit with metal layer having carbon nanotubes and methods of making same.
  8. Dubin,Valery M.; Moon,Peter K., Method and apparatus for an improved air gap interconnect structure.
  9. Dubin, Valery M.; Moon, Peter K., Method for an improved air gap interconnect structure.
  10. McFeely, Fenton R.; Yang, Chih-Chao, Method for improving the selectivity of a CVD process.
  11. Kim, Sang Chul; Han, Jae Won, Method for manufacturing semiconductor device.
  12. Ivanov, Igor C.; Zhang, Weiguo; Kolics, Artur, Method for strengthening adhesion between dielectric layers formed adjacent to metal layers.
  13. Zhong,Ting; Hua,Fay; Dubin,Valery M., Methods to deposit metal alloy barrier layers.
  14. Stephanou, Philip Jason; Burns, David William; Shenoy, Ravindra V., Microspeaker with piezoelectric, metal and dielectric membrane.
  15. Cheng,Chin Chang; Dubin,Valery M., Multiple stage electroless deposition of a metal layer.
  16. Stephanou, Philip Jason; Burns, David William, Piezoelectric microphone fabricated on glass.
  17. Stephanou, Philip Jason; Burns, David William, Piezoelectric microphone fabricated on glass.
  18. Yabe, Atsushi; Ito, Junichi; Hisumi, Yoshiyuki; Sekiguchi, Junnosuke; Imori, Toru, Plated article having metal thin film formed by electroless plating, and manufacturing method thereof.
  19. Yang,Chih Chao; Gaudet,Simon; Lavoie,Christian; Ponoth,Shom; Spooner,Terry A., Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement.
  20. Yang,Chih Chao; Gaudet,Simon; Lavoie,Christian; Ponoth,Shom; Spooner,Terry A., Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement.
  21. Christenson, Kurt Karl, Reagent activator for electroless plating.
  22. Christenson,Kurt Karl, Reagent activator for electroless plating.
  23. Andricacos,Panayotis C.; Chen,Shyng Tsong; Cotte,John M.; Deligianni,Hariklia; Krishnan,Mahadevaiyer; Tseng,Wei Tsu; Vereecken,Philippe M., Selective capping of copper wiring.
  24. Andricacos,Panayotis C.; Chen,Shyng Tsong; Cotte,John M.; Deligianni,Hariklia; Krishnan,Mahadevaiyer; Tseng,Wei Tsu; Vereecken,Philippe M., Selective capping of copper wiring.
  25. Lee, Jae Suk, Semiconductor devices and methods for manufacturing the same.
  26. Wan, Wen-Kai; Lin, Yih-Hsiung; Lei, Ming-Ta; Perng, Baw-Ching; Lin, Cheng-Chung; Lin, Chia-Hui; Liu, Ai-Sen, Surface treatment of metal interconnect lines.
  27. Stephanou, Philip Jason; Burns, David William; Shenoy, Ravindra V., Transducer with piezoelectric, conductive and dielectric membrane.
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