A distributed electronic warfare system includes a central control site for controlling and receiving data from the system and utilizes a satellite communications system for communications within the system. Electronic warfare pods are attached to variety of aircraft. The electronic warfare pods lis
A distributed electronic warfare system includes a central control site for controlling and receiving data from the system and utilizes a satellite communications system for communications within the system. Electronic warfare pods are attached to variety of aircraft. The electronic warfare pods listen to signals from targets and jam the targets under control of the central control site. The pods supply the data to the central control site. The pods have antennas for radiating jamming signals to the targets and receiving signals from the targets. Transmitters in the pods generate jamming signals and receivers receive the signals from the targets. A signal processor processes the received signals from the targets. The pods may be used for search and collection, geolocation, and electronic attack under control of the central control site.
대표청구항▼
A distributed electronic warfare system includes a central control site for controlling and receiving data from the system and utilizes a satellite communications system for communications within the system. Electronic warfare pods are attached to variety of aircraft. The electronic warfare pods lis
A distributed electronic warfare system includes a central control site for controlling and receiving data from the system and utilizes a satellite communications system for communications within the system. Electronic warfare pods are attached to variety of aircraft. The electronic warfare pods listen to signals from targets and jam the targets under control of the central control site. The pods supply the data to the central control site. The pods have antennas for radiating jamming signals to the targets and receiving signals from the targets. Transmitters in the pods generate jamming signals and receivers receive the signals from the targets. A signal processor processes the received signals from the targets. The pods may be used for search and collection, geolocation, and electronic attack under control of the central control site. ltage of the input signal with a second reference voltage for determining if the voltage of the input signal is below a lower operating voltage limit of the operating voltage range of the buffer circuit, the first reference voltage being higher than the second reference voltage. 8. A conditioning circuit as claimed in claim 5 in which the buffer circuit comprises a first buffer circuit and a second buffer circuit connected in parallel, each of the first and second buffer circuits operable within a respective operating voltage range, said operating voltage ranges overlapping such that the operating voltage range within which the first buffer circuit is operable has an upper operating voltage limit higher than the upper operating voltage limit of the second buffer circuit and the operating voltage range of the second buffer circuit has a lower operating voltage limit lower than the lower operating voltage limit of the first buffer circuit, the respective first and second buffer circuits being alternately selectable so that if the voltage of the input signal exceeds the upper operating voltage limit of the second buffer circuit, the input signal is passed through the first buffer circuit, and if the voltage of the input signal falls below the lower operating voltage limit of the first buffer circuit, the input signal is passed through the second buffer circuit. 9. A conditioning circuit as claimed in claim 8 in which the control circuit comprises a secondary comparator for comparing the voltage of the input signal with an intermediate reference voltage, the control circuit being responsive to the secondary comparator for selecting one of the first and second buffer circuits for passing the input signal to the signal processing circuit. 10. A conditioning circuit as claimed in claim 9 in which the intermediate reference voltage is selected to lie between the lower operating voltage limit of the first buffer circuit and the upper operating voltage limit of the second buffer circuit. 11. A conditioning circuit as claimed in claim 1 in which a primary switching circuit is provided for selectively switching the input signal through the one of the buffer circuit and the bypass circuit, the primary switching circuit being responsive to the control circuit for selecting the one of the buffer circuit and the bypass circuit through which the input signal is to be passed to the signal processing circuit. 12. A conditioning circuit as claimed in claim 11 in which the primary switching circuit comprises a first primary switch located in the buffer circuit for isolating the buffer circuit from the signal processing circuit, and a second primary switch located in the bypass circuit for isolating the bypass circuit from the signal processing circuit, the respective first and second primary switches being responsive to the control circuit such that when one of the first and second primary switches is in a closed circuit state for selecting the corresponding one of the buffer circuit and the bypass circuit, the other of the first and second primary switches is in an open circuit state. 13. A conditioning circuit as claimed in claim 8 in which a secondary switching circuit is provided for selectively passing the input signal through one of the first and second buffer circuits. 14. A conditioning circuit as claimed in claim 1 in which the conditioning circuit is implemented as an integrated circuit. 15. A conditioning circuit as claimed in claim 1 in which the conditioning circuit is adapted for selectively buffering the input signal to an analog to digital converter. 16. A circuit comprising: a signal processing circuit for processing a plurality of input signals, a main switch circuit for selectively switching at least one of the plurality of input signals to the signal processing circuit, and at least one conditioning circuit for selectively buffering the input signals received from the main switch circuit to the signal processing circuit, e ach conditioning circuit comprising: a buffer circuit operable within an operating voltage range, for buffering the input signals, a bypass circuit for selectively bypassing the buffer circuit, and a control circuit for selecting one of the buffer circuit and the bypass circuit for passing the selected input signals to the signal processing circuit, so that the input signals, voltages of which fall outside said operating voltage range, are passed to the signal processing circuit through the bypass circuit. 17. A circuit as claimed in claim 16 in which the signal processing circuit comprises two input terminals for receiving positive signals of the selected input signals and negative signals of the selected input signals from the main switch circuit, and the conditioning circuit is located for passing the positive or negative signals of the selected input signals from the main switch circuit to one of the input terminals of the signal processing circuit. 18. A circuit as claimed in claim 17 in which one of the input terminals of the signal processing circuit is a positive input terminal, and the other input terminal of the signal processing circuit is a negative input terminal, and two conditioning circuits are provided, one conditioning circuit being located for passing either the positive or negative signals of the selected input signals from the main switch circuit to the positive input terminal of the signal processing circuit, and the other conditioning circuit being located for passing the others of the positive and negative signals of the selected input signals from the main switch circuit to the negative input terminal of the signal processing circuit. 19. A circuit as claimed in claim 18 in which the main switch circuit is operable for alternately applying the positive and negative signals of the selected input signals to each of the positive and negative input terminals of the signal processing circuit. 20. A circuit as claimed in claim 16 in which the main switch circuit is responsive to a select signal for selecting the input signals, and the control circuit of each conditioning circuit is responsive to the select signal for selecting the one of the buffer circuit and the bypass circuit. 21. A circuit as claimed in claim 16 in which the control circuit of each conditioning circuit is responsive to the voltage of the selected input signal received by the conditioning circuit for selecting the one of the buffer circuit and the bypass circuit. 22. A circuit as claimed in claim 21 in which the control circuit of each conditioning circuit comprises a primary comparing circuit for comparing the voltage of the input signal received by the conditioning circuit with a reference voltage for determining if the voltage of the input signal is within the operating voltage range of the buffer circuit, and the control circuit is responsive to the primary comparing circuit for selecting the one of the buffer circuit and the bypass circuit. 23. A circuit as claimed in claim 22 in which the primary comparing circuit of each conditioning circuit comprises a first primary comparator for comparing the voltage of the input signal received by the conditioning circuit with a first reference voltage for determining if the voltage of the input signal exceeds an upper operating voltage limit of the operating voltage range of the buffer circuit, and a second primary comparator for comparing the voltage of the input signal with a second reference voltage for determining if the voltage of the input signal is below a lower operating voltage limit of the operating voltage range of the buffer circuit, the first reference voltage being higher than the second reference voltage. 24. A circuit as claimed in claim 21 in which the buffer circuit of each conditioning circuit comprises a first buffer circuit and a second buffer circuit connected in parallel, the first and second buffer circuits having respective overlapping operating voltage ranges,
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