초록 ▼

A non-linear magnetic harmonic motion converter apparatus for transferring non-linear motion into rotational motion for producing work from an interaction of at least two magnetic fields. An axial shaft is disposed in rotating relationship with at least one gimbal supported magnet that reciprocates

A non-linear magnetic harmonic motion converter apparatus for transferring non-linear motion into rotational motion for producing work from an interaction of at least two magnetic fields. An axial shaft is disposed in rotating relationship with at least one gimbal supported magnet that reciprocates in relation to the axial shaft. At least one rotor magnet is disposed to rotate in relation to the axial shaft in response to non-linear movement of the at least one gimbal supported magnet. A plurality of rotor magnet units may be proximally disposed to rotate about separate axial shafts, with each rotor magnet unit having a rotor magnetic field influenced by the non-linear movement of the at least one gimbal supported magnet disposed proximal to each rotor magnet unit. Movement of the each gimbal supported magnet creates repulsion and attraction of each respective rotor magnet, with inducement of axial shaft rotation, thereby producing rotational movement that is harnessed to perform work. Also disclosed are combinations of rotor magnet units disposed to rotate about respective axial shafts upon the reciprocation of a central gimbal supported magnet, for utilization in the operation of a fluid transfer pump and/or an electric generator.

대표청구항 ▼

A non-linear magnetic harmonic motion converter apparatus for transferring non-linear motion into rotational motion for producing work from an interaction of at least two magnetic fields. An axial shaft is disposed in rotating relationship with at least one gimbal supported magnet that reciprocates

A non-linear magnetic harmonic motion converter apparatus for transferring non-linear motion into rotational motion for producing work from an interaction of at least two magnetic fields. An axial shaft is disposed in rotating relationship with at least one gimbal supported magnet that reciprocates in relation to the axial shaft. At least one rotor magnet is disposed to rotate in relation to the axial shaft in response to non-linear movement of the at least one gimbal supported magnet. A plurality of rotor magnet units may be proximally disposed to rotate about separate axial shafts, with each rotor magnet unit having a rotor magnetic field influenced by the non-linear movement of the at least one gimbal supported magnet disposed proximal to each rotor magnet unit. Movement of the each gimbal supported magnet creates repulsion and attraction of each respective rotor magnet, with inducement of axial shaft rotation, thereby producing rotational movement that is harnessed to perform work. Also disclosed are combinations of rotor magnet units disposed to rotate about respective axial shafts upon the reciprocation of a central gimbal supported magnet, for utilization in the operation of a fluid transfer pump and/or an electric generator. respectively connected to the bit line pairs are respectively in contact with the first contact line and the first contacts are formed where the first contact line and the bit line pairs cross each other. 4. The structure, as defined in claim 2, wherein the active regions of the first and second transistors respectively connected with the section data line pairs are in contact with the second contact line and the second contacts are formed where the second contact line and the section data line pairs cross each other. 5. The structure, as defined in claim 1, wherein the first and second transistors are write path NMOS transistors and read path PMOS transistors, respectively. 6. The structure, as defined in claim 2, wherein the section data line pairs, which are made of a metal identical with the bit lines, are arranged in parallel to the bit line pairs. 7. The structure, as defined in claim 1, wherein the first and second transistors are arranged in a multi-row structure of predetermined length within an area occupied by a predetermined total number of memory cells. 8. The structure, as defined in claim 1, wherein the first and second transistors are arranged in a multi-column and multi-row matrix structure of a predetermined dimension with a predetermined number of transistors. 9. The structure, as defined in claim 8, wherein the first and second transistors are arranged in a predetermined top/bottom sequence with the first transistors for bit lines and the second transistors for bit line bars. 10. The structure, as defined in claim 7, wherein spaces of predetermined size are formed for gate signals at both sides of the predetermined number of memory cell columns within the area occupied by the total memory cells in the arrangement of the first and second transistors. 11. The structure, as defined in claim 6, wherein the first metal is aluminum. 12. The structure, as defined in claim 3, wherein the first contact line comprises tungsten. 13. The structure, as defined in claim 4, wherein the second contact line comprises tungsten. 14. A column path layout structure of a semiconductor memory device comprising: bit line pairs respectively connected to a plurality of memory cells at a predetermined gap between the memory cells in parallel to a Y-axis; and active regions of write path NMOS transistors and those of read path PMOS transistors longitudinally formed in perpendicular to the bit line pairs, wherein active regions of the write path NMOS transistors and those of read path PMOS transistors are longitudinally arranged in perpendicular to the bit line pairs, and wherein the write path NMOS transistors and the read path PMOS transistors are respectively arranged over and under the bit line pairs, and wherein the write and read column path layout structure further comprises: section data line pairs positioned in parallel to the bit line pairs; first contact lines of a metal conductivity layer are positioned under the bit line pairs to be in contact with the section data line pairs through the second contact; second contact lines of a metal conductivity layer are positioned under the bit line pairs to be in contact with the section data line pairs through the second contact; and transistors positioned under the contact lines, the transistors having gates and drain and source active regions, the active regions being arranged in perpendicular to the longitudinal direction of the bit line pairs, wherein first side regions of the drain/source active regions are in contact with the first contact lines that cross the bit line pairs to be connected in a saw-like shape mesh through the first contact at an edge, another side region of the drain/source active regions being shared with the transistors of adjacent memory cells and, being in contact with the second contact lines via the second contact, wherein the second contact lines and section data line pairs cross each other and are connected with the section data line pairs, and the transistors forming spaces of a predetermined size at both sides of the column path having a predetermined number of memory cells within the area of the predetermined number of total memory cells, the first transistors for bit lines and the second transistors for bit line bars being arranged in a top/bottom sequence and being connected with the bit line pair. 15. The structure, as defined in claim 14, wherein the active regions of the write path NMOS transistors and read path PMOS transistors are arranged in perpendicular to the longitudinal direction of the bit line pairs, and wherein the read path PMOS transistors are positioned over the bit line pairs and the write path NMOS transistors are positioned under the bit line pairs. 16. The structure, as defined in claim 14, wherein the active regions of the write path NMOS transistors, which are positioned over the bit line pairs, are arranged in perpendicular to the longitudinal direction of the bit line pairs, and wherein the active regions of the read column path PMOS transistors, which are positioned under the bit line pairs, are arranged in parallel to the longitudinal direction of the bit line pairs. 17. The structure, as defined in claim 15, wherein the write and read column path layout structure further comprises: section data line pairs positioned in parallel to the bit line pairs; first contact lines of a metal conductivity layer being positioned under of the bit line pairs to be in contact with the section data line pairs through the second contact; second contact lines of a metal conductivity layer being positioned under the bit line pairs to be in contact with the section data line pairs through the second contact; and transistors positioned under the contact lines, the transistors having gates and drain and source active regions, the active regions being arranged in perpendicular to the longitudinal direction of the bit line pairs, wherein first side regions of the drain/source active regions are in contact with the first contact lines that cross the bit line pairs to be connected in a saw-like shape mesh through the first contact at an edge, another side region of the drain/source active regions being shared with the transistors of adjacent memory cells and being in contact with the second contact lines via the second contact, wherein the second contact lines and section data line pairs cross each other and are connected with the section data line pairs, and the transistors forming spaces of a predetermined size at both sides of the column path having a predetermined number of memory cells within the area of the predetermined number of total memory cells, the first transistors for bit lines and the second transistors for bit line bars being arranged in a top/bottom sequence and being connected with the bit line pairs. 18. The structure, as defined in claim 16, wherein the write column path layout structure comprises: section data line pairs arranged in parallel to the bit line pairs; the first contact lines of a metal conductivity layer being positioned under the bit line pairs to be in contact with the bit line pairs through the first contact; and the second contact lines of metal conductivity layer being positioned under the bit line pairs to be in contact with the section data line pairs through the second contact; transistors being arranged under the contact lines, the transistors having gates, drain regions and source regions, the active regions being arranged in perpendicular to the longitudinal direction of the bit line pairs, the drain regions being respectively in contact with the first contact lines cross the bit line pairs through the first contacts to be in a saw-like shape at an edge, adjacent drain regions being in the form of a mesh, the source regions being shared with the transistors of adjacent memory cells and being in contact with the second contact lines via the second contact, wherein the second contact lines and the section data line pairs cross one another, the adjustment drain regions further being connected to the section data line pairs, and the transistors forming spaces of predetermined size at both sides of the column of a predetermined number of memory cells within the area of the predetermined total number of memory cells, the first transistors for bit lines and the second transistors for bit line bars being arranged in a top/bottom sequence and being connected with the bit line pairs.