Integrated micromachine relay for automated test equipment applications
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G01R-031/02
출원번호
US-0859842
(2001-05-16)
발명자
/ 주소
Smith, Stephen W.
Creek, William R.
출원인 / 주소
LTX Corporation
대리인 / 주소
Blakely, Sokoloff, Taylor & Zafman LLP
인용정보
피인용 횟수 :
8인용 특허 :
24
초록▼
A method and apparatus for a micromachine relay is provided. A pin controller comprises at least one spring pin designed to movably couple the pin controller to a device under test (DUT) to provide signals to the DUT. The pin controller further includes a micromachine relay coupled to the at least o
A method and apparatus for a micromachine relay is provided. A pin controller comprises at least one spring pin designed to movably couple the pin controller to a device under test (DUT) to provide signals to the DUT. The pin controller further includes a micromachine relay coupled to the at least one spring pin to control the movement of the at least one spring pin and an integrated circuit for controlling the micromachine relay.
대표청구항▼
1. An integrated circuit card for a test head, the integrated circuit card comprising: an input/output (I/O) channel with an elastomeric connector; pin electronics integrated circuit (PEIC) coupled to the I/O channel; micromachine relays coupled to the PEIC; spring pins coupled to and controll
1. An integrated circuit card for a test head, the integrated circuit card comprising: an input/output (I/O) channel with an elastomeric connector; pin electronics integrated circuit (PEIC) coupled to the I/O channel; micromachine relays coupled to the PEIC; spring pins coupled to and controlled by the micromachine relays, the spring pins designed to be movably coupled to a device under test (DUT); a heat sink structure integral to the integrated circuit card to flow a chilled substance through the heat sink structure to cool the PEICs. 2. The integrated circuit card of claim 1, wherein the chilled substance comprises a gas or a liquid. 3. The integrated circuit card of claim 1, wherein the heat sink structure comprises cooling channels within the integrated circuit card. 4. The integrated circuit card of claim 1, wherein the cooling channels are etched, drilled, cast, or micromachined within the integrated circuit card. 5. The integrated circuit card of claim 1, further comprising a driver circuit for driving a movement of each of the micromachine relays. 6. The integrated circuit card of claim 1, wherein the integrated circuit card further includes a timing generator for generating clocking and timing signals for the PEIC. 7. The integrated circuit card 6, wherein the timing generator is located on the test head, thereby reducing signal delays. 8. The integrated circuit card of claim 1, further comprising a tester for generating the signals used to test the DUT. 9. The integrated circuit card of claim 8, further comprising a logic circuit receiving signals from the tester. 10. The integrated circuit card of claim 9, wherein the logic circuit is located on the test head. 11. The integrated circuit card of claim 9, wherein the logic circuit is a field programmable gate array (FPGA). 12. A circuit card for a test head, the circuit card comprising: an input/output channel with a connector; a pin electronics integrated circuit (PEIC) coupled to the input/output channel; micromachine relays coupled to the PEIC; spring pins coupled to and controlled by the micromachine relays, the spring pins designed to be movably coupled to a device under test (DUT). 13. The circuit card of claim 12, further comprising a driver circuit for driving movements of the micromachine relays. 14. The circuit card of claim 12, wherein the circuit card further includes a timing generator for generating clocking and timing signals for the PEIC. 15. The circuit card of claim 14, wherein the timing generator is located on the test head, thereby reducing signal delays. 16. The circuit card of claim 12, further comprising a tester for generating the signals used to test the DUT. 17. The circuit card of claim 16, further comprising a logic circuit receiving signals from the tester. 18. The circuit card of claim 17, wherein the logic circuit is located on the test head. 19. The circuit card of claim 17, wherein the logic circuit is a field programmable gate array (FPGA). 20. A circuit card for a test head, the circuit card comprising: input/output means with connector means; pin electronics means coupled to the input/output means; micromachine relay means coupled to the pin electronics means; spring means controlled by the micromachine relay means for movable coupling to a device under test. 21. The circuit card of claim 20, further comprising means for driving movement of the micromachine relay means. 22. The circuit card of claim 20, further comprising means for generating clocking and timing signals for the pin electronics means. 23. The circuit card of claim 20, further comprising means for generating signals for testing the device under test.
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