IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
|
출원번호 |
US-0957820
(2001-09-20)
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발명자
/ 주소 |
- Salvi, Rohan S.
- Howard, Michael A.
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출원인 / 주소 |
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대리인 / 주소 |
Wadsworth, PhilipBaker, KentGodsey, Sandra L.
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인용정보 |
피인용 횟수 :
5 인용 특허 :
4 |
초록
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A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. Th
A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. The memory receives and stores unpunctured ones of the MR code bits from the first encoder. The second encoder receives and codes N code bits in parallel in accordance with a second coding scheme to generate coded data. M and N can be any values (e.g., M≥8, N≥4). Each encoder can be a (e.g., a rate 1/2) convolutional encoder that implements a particular polynomial generator, and can be implemented with one or more look-up tables, a state machine, or some other design.
대표청구항
▼
A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. Th
A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. The memory receives and stores unpunctured ones of the MR code bits from the first encoder. The second encoder receives and codes N code bits in parallel in accordance with a second coding scheme to generate coded data. M and N can be any values (e.g., M≥8, N≥4). Each encoder can be a (e.g., a rate 1/2) convolutional encoder that implements a particular polynomial generator, and can be implemented with one or more look-up tables, a state machine, or some other design. r correction unit are carried out by two memories and by said controller. 3. A storage device as claimed in claim 2, wherein in response to said read command received by said system interface unit, one of said two memories originates said data after the error detection and error correction operation and another of said two memories originates said subsequent data for the error detection and error correction operation. 4. A storage device as claimed in claim 3, wherein said one and said other of said two memories are said non-volatile semiconductor memory. 5. A storage device as claimed in claim 4, wherein said non-volatile semiconductor memory is a flash memory. 6. A storage device as claimed in claim 5, wherein said one of said two memories is coupled with said error correction unit via a first memory bus, said other of said two memories is coupled with said error correction unit via a second memory bus, wherein during said data transfer of said data after said error detection and error correction operation, said data after said error detection and error correction operation is transferred to said host system via said system interface and said subsequent data for said error detection and error correction operation is transferred from said other of said two memories to said error correction unit via said second memory bus, and wherein during said data transfer of said subsequent data after said error detection and error correction operation, said subsequent data after said error detection and error correction operation is transferred to said host system via said system interface and further subsequent data for the error detection and error correction operation is transferred from said one of said two memories to said error correction unit via said first memory bus. 7. A storage device as claimed in claim 4, wherein said one of said two memories is coupled with said error correction unit via a first memory bus, said other of said two memories is coupled with said error correction unit via a second memory bus, wherein during said data transfer of said data after said error detection and error correction operation, said data after said error detection and error correction operation is transferred to said host system via said system interface and said subsequent data for said error detection and error correction operation is transferred from said other of said two memories to said error correction unit via said second memory bus, and wherein during said data transfer of said subsequent data after said error detection and error correction operation, said subsequent data after said error detection and error correction operation is transferred to said host system via said system interface and further subsequent data for the error detection and error correction operation is transferred from said one of said two memories to said error correction unit via said first memory bus. 8. A storage device as claimed in claim 2, wherein said one and said other of said two memories are said non-volatile semiconductor memory. 9. A storage device as claimed in claim 8, wherein said non-volatile semiconductor memory is a flash memory. 10. A storage device as claimed in claim 9, wherein said one of said two memories is coupled with said error correction unit via a first memory bus, said other of said two memories is coupled with said error correction unit via a second memory bus, wherein during said data transfer of said data after said error detection and error correction operation, said data after said error detection and error correction operation is transferred to said host system via said system interface and said subsequent data for said error detection and error correction operation is transferred from said other of said two memories to said error correction unit via said second memory bus, and wherein during said data transfer of said subsequent data after said error detection and error correction operation, said sub
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