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A semiconductor chip including a bump projecting from a surface protective film thereof and a surface interconnection having a smaller height than the bump. The surface interconnection may project from the surface protective film or may be flush with the surface protective film. The surface intercon

A semiconductor chip including a bump projecting from a surface protective film thereof and a surface interconnection having a smaller height than the bump. The surface interconnection may project from the surface protective film or may be flush with the surface protective film. The surface interconnection may be connected to the bump. The bump may include a peripheral bump configured as surrounding a device formation region of the chip. The peripheral bump may be connected to the ground or a power source.

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1. A semiconductor chip, comprising: a substrate; at least one internal interconnection connected to the substrate; a surface protective film covering the substrate and partially covering the at least one internal interconnection to form a partially exposed portion of the at least one internal

1. A semiconductor chip, comprising: a substrate; at least one internal interconnection connected to the substrate; a surface protective film covering the substrate and partially covering the at least one internal interconnection to form a partially exposed portion of the at least one internal interconnection; a bump electrically connected to the at least one internal interconnection via the partially exposed portion and projecting outwardly from the surface protection film to define a height from the surface protection film; an electrically conductive element; and a surface interconnection integrally formed with the bump and disposed such that at least a portion of the surface protection film is sandwiched between the surface interconnection and the substrate, the surface interconnection extending laterally relative to the bump across the semiconductor chip and outwardly relative to the surface protection film yet positioned below the height of the bump to electrically connect the bump and the electrically conductive element, wherein the electrically conductive element is another at least one internal interconnection. 2. A semiconductor chip as set forth in claim 1, which is to be bonded onto a surface of a solid body, wherein the surface protective film covers a surface of the semiconductor chip which is opposed to the surface of the solid body, and wherein the bump is an electrical connection of the semiconductor chip to the solid body. 3. A semiconductor chip as set forth in claim 1, wherein the bump includes a peripheral bump which is provided outside a device formation region of a semiconductor substrate which is a base body of the semiconductor chip. 4. A semiconductor chip as set forth in claim 3; wherein the peripheral bump surrounds the device formation region. 5. A semiconductor chip as set forth in claim 3, wherein the peripheral bump is provided in a scribe line region. 6. A semiconductor chip as set forth in claim 3 wherein the surface interconnection is connected to the peripheral bump. 7. A semiconductor chip as set forth in claim 3 wherein the peripheral bump is connected to a ground or a power source. 8. A semiconductor chip as set forth in claim 1, wherein the substrate is an inter-level insulating film. 9. A semiconductor chip as set forth in claim 1, wherein the electrically conductive element is a peripheral bump. 10. A semiconductor chip as set forth in claim 9, wherein the peripheral bump is one of a grounding bump and a power supply bump. 11. A semiconductor chip as set forth in claim 1, further comprising a barrier metal film and a seed film, the barrier metal film covering the surface protection film and the seed film covering the barrier metal film, the surface interconnection contacting the seed film. 12. A semiconductor chip as set forth in claim 1, wherein the surface interconnection is formed with the same material added that of the bump.