Microprocessor extensions for two-dimensional graphics processing
IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0409819
(1999-09-30)
|
발명자
/ 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
Procopio Cory Hargreaves & Savitch
|
인용정보 |
피인용 횟수 :
7 인용 특허 :
6 |
초록
▼
Embodiments of the invention comprise a new device and technique to realize an improved graphics generation system. This improvement is preferably achieved by implementing an interface logic portion to interface with the CPU, a control register portion, a pixel FIFO array portion, a pixel processing
Embodiments of the invention comprise a new device and technique to realize an improved graphics generation system. This improvement is preferably achieved by implementing an interface logic portion to interface with the CPU, a control register portion, a pixel FIFO array portion, a pixel processing logic portion, and a control logic portion. These portions are preferably implemented as an extension of the internal architecture of the CPU. The CPU may be attached to the graphics system via a data cache and a write buffer portion. Data is read from the system memory and placed in the data cache so that subsequent accesses to the same location only require access to the cache. System memory data is written to a write buffer, so that the data written may be queued up and sent to the main memory at an appropriate time. The display refresh controller also reads the data from the system memory and converts the data to a signal for output to a display.
대표청구항
▼
Embodiments of the invention comprise a new device and technique to realize an improved graphics generation system. This improvement is preferably achieved by implementing an interface logic portion to interface with the CPU, a control register portion, a pixel FIFO array portion, a pixel processing
Embodiments of the invention comprise a new device and technique to realize an improved graphics generation system. This improvement is preferably achieved by implementing an interface logic portion to interface with the CPU, a control register portion, a pixel FIFO array portion, a pixel processing logic portion, and a control logic portion. These portions are preferably implemented as an extension of the internal architecture of the CPU. The CPU may be attached to the graphics system via a data cache and a write buffer portion. Data is read from the system memory and placed in the data cache so that subsequent accesses to the same location only require access to the cache. System memory data is written to a write buffer, so that the data written may be queued up and sent to the main memory at an appropriate time. The display refresh controller also reads the data from the system memory and converts the data to a signal for output to a display. ischarge by applying a first pulse in which an applied voltage varies with time, and a second step of applying a second pulse in which an applied voltage varies with time so as to adjust a magnitude of wall charges produced with said first pulse, wherein these first and second steps are carried out during said field reset charge adjustment period. 12. A method for driving a plasma display panel in which pluralities of first electrodes and second electrodes are arranged in parallel to each other and adjacently, a plurality of third electrodes is arranged to cross the pairs of first and second electrodes at electrode crossing areas and to define corresponding discharge cells at the electrode crossing areas and wherein, during a reset period, each of the discharge cells is initialized during an addressing period, wall charges are provided in the discharge cells according to display data and, during a sustain discharge period, sustain discharges are induced in discharge cells in which wall charges are provided during the addressing period, said method for driving a plasma display panel comprising, during said reset period: applying a first pulse in which an applied voltage varies with time until reaching a first potential so as to induce a first discharge in the discharge cells of respective display lines defined by said first and second electrodes, said first pulse having a predetermined polarity with respect to the second potential that is the potential attained before the application of said first pulse; and applying a second pulse, in which an applied voltage varies with time so as to induce a second discharge, as an erase discharge, in the discharge cells of the respective display lines defined by said first and second electrodes, said second pulse having a polarity opposite to the predetermined polarity of said first pulse with respect to said second potential. 13. A method for driving a plasma display panel according to claim 12, wherein each of said first and second pulses in which an applied voltage varies with time is a slope pulse whose voltage variation per unit time changes in magnitude. 14. A method for driving a plasma display panel according to claim 12, wherein each of said first and second pulses in which an applied voltage varies with time is a triangular wave whose voltage variation per unit time is constant in magnitude. 15. A method for driving a plasma display panel according to claim 12, wherein
이 특허에 인용된 특허 (6)
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Atsushi Kunimatsu JP, Apparatus having graphic processor for high speed performance.
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Leung Wingyu ; Tam Kit Sang, Caching method and circuit for a memory system with circuit module architecture.
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Hsu Hsi-Yuan (Shindan TWX), Display device controller and method.
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Laksono Indra,CAX ; Asaro Anthony,CAX, Method and apparatus for co-processing multi-formatted data.
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Suzuoki Masakazu,JPX ; Furuhashi Makoto,JPX ; Tanaka Masayoshi,JPX ; Yutaka Teiji,JPX, Method of producing image data and associated recording medium.
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Hirano Tetsuya,JPX ; Kunigita Hisayuki,JPX ; Okamoto Shinichi,JPX ; Noda Shinji,JPX ; Yutaka Teiji,JPX, Video signal reproducing apparatus.
이 특허를 인용한 특허 (7)
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Lapham, John R., Automation equipment control system.
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Lapham, John R., Automation equipment control system.
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Lapham, John R., Automation equipment control system.
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Sasaki, Nobuo; Shimizu, Masao, Multi-graphics processor system, graphics processor and data transfer method.
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Hiroi, Toshiyuki; Oka, Masaaki, Multi-graphics processor system, graphics processor and rendering method.
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Marino, Charles F., Raster operation unit.
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Hsieh,Phil, System and method for accelerating two-dimensional graphics in a computer system.
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