초록 ▼

The present invention relates to a method and apparatus for efficiently managing the I/O design of an integrated circuit. The present invention automatically selects and interconnects a number of I/O cells selected from a design library to form an I/O interface. A user interface is provided for rece

The present invention relates to a method and apparatus for efficiently managing the I/O design of an integrated circuit. The present invention automatically selects and interconnects a number of I/O cells selected from a design library to form an I/O interface. A user interface is provided for receiving a number of parameters provided by the circuit designer. The parameters preferably provide specific information about a circuit design. A set of circuit design assembly rules are also provided, which define the available I/O cells and the appropriate interconnections of the available I/O cells. A computer program then selects and assembles the I/O cells in accordance with the user provided parameters and the set of circuit design assembly rules.

대표청구항 ▼

The present invention relates to a method and apparatus for efficiently managing the I/O design of an integrated circuit. The present invention automatically selects and interconnects a number of I/O cells selected from a design library to form an I/O interface. A user interface is provided for rece

The present invention relates to a method and apparatus for efficiently managing the I/O design of an integrated circuit. The present invention automatically selects and interconnects a number of I/O cells selected from a design library to form an I/O interface. A user interface is provided for receiving a number of parameters provided by the circuit designer. The parameters preferably provide specific information about a circuit design. A set of circuit design assembly rules are also provided, which define the available I/O cells and the appropriate interconnections of the available I/O cells. A computer program then selects and assembles the I/O cells in accordance with the user provided parameters and the set of circuit design assembly rules. hod carried out in a computer, for verifying design of a system having a set of properties, and a given set of variables, where each variable in said set of variables has a permissible range of values, where said verifying of the system is carried out by verifying each property, and where verifying a property is carried out by reducing a specification of said system design with respect to said property by eliminating values from said ranges of values of said variables, up to and including completely eliminating one or more of said variables, forming thereby a reduced system, and performing the verification on the reduced system design relative to a model of said system, the improvement comprising: selecting from said set of properties a property that needs to be verified, performing a verification operation with respect to said property selected in said step of selecting; when said verification operation concludes that the property is not verified, creating a modified system design and system model, and returning to said step of performing; when said verification operation concludes that the property is verified, storing ranges of values employed in connection with variables from said set of variables that are employed in said step of performing, not commingled with stored ranges of values pertaining to other properties, and determining whether previously verified properties need to be re-verified; when said determining concludes that previously verified properties need to be reverified, returning to said step of selecting; when said determining concludes that previously verified properties need not be re-verified, returning to said step of selecting, but only as long as there are properties in said set of properties that need to be verified; and when there are no properties in said set of properties that need to be verified, reporting-out on ranges of said variables that are employed in said steps of verification operation.