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Adhesive layer for an electronic apparatus having multiple semiconductor devices 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/54
출원번호 US-0505018 (2000-02-16)
발명자 / 주소
  • Boon, Suan Jeung
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner & Kluth, P.A.
인용정보 피인용 횟수 : 36  인용 특허 : 59

초록

Flip chip packages and methods for producing a flip chip package by prepackaging one or more dice on a semiconductor wafer. The package, in one embodiment, includes an adhesive layer applied to an active side of the wafer. The adhesive layer has openings to permit access to the conductive pads on ea

대표청구항

Flip chip packages and methods for producing a flip chip package by prepackaging one or more dice on a semiconductor wafer. The package, in one embodiment, includes an adhesive layer applied to an active side of the wafer. The adhesive layer has openings to permit access to the conductive pads on ea

이 특허에 인용된 특허 (59)

  1. Knuth Kenneth V. (Malvern PA) Drinkard ; Jr. John H. (Exton PA), Apparatus and method for inserting solder preforms on selected circuit board back plane pins.
  2. Williams Ronald L. (San Marcos CA) Tyra Joe B. (Carlsbad CA), Apparatus and method for protecting metal bumped integrated circuit chips during processing and for providing mechanical.
  3. Akram Salman, Apparatus for packaging flip chip bare die on printed circuit boards.
  4. Murphy James V., Ball grid array including modified hard ball contacts and apparatus for attaching hard ball contacts to a ball grid arra.
  5. Lemke ; Timothy Allen ; Shultz ; Jr. ; Edmond Franklin, Carrier strip mounted electrical components.
  6. Brooks Jerry M. ; Thummel Steven G., Cavity ball grid array apparatus.
  7. Nakamura Yoshifumi,JPX ; Bessho Yoshihiro,JPX ; Itagaki Minehiro,JPX, Chip carrier.
  8. Allen Leslie J. (Swindon CA GB2) Cherian Gabe (Fremont CA) Diaz Stephen H. (Los Altos CA), Chip carrier mounting device.
  9. Allen Leslie J. (Swindon CA GB2) Cherian Gabe (Fremont CA) Diaz Stephen H. (Los Altos CA), Chip mounting device.
  10. Ball Michael B., Combination of semiconductor interconnect.
  11. Ball Michael B., Combination of semiconductor interconnect.
  12. Solberg Vernon, Compliant multichip package.
  13. Tsukagoshi Isao (Shimodate) Yamaguchi Yutaka (Yuki) Nakajima Atsuo (Ibaraki) Goto Yasushi (Shimodate JPX), Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips.
  14. Akram Salman, Conductive bumps on die for flip chip application.
  15. Svendsen ; Leo G. (Redwood City CA) Leary Rebecca A. (Milpitas CA) Geschwind Gary I. (Palo Alto CA), Connection to a component for use in an electronics assembly.
  16. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  17. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  18. Wark James M. (Boise ID), Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
  19. Hoffman Paul R. ; Popplewell James M. ; Braden Jeffrey S., Edge connectable metal package.
  20. Gilleo Ken, Flip chip with integrated flux and underfill.
  21. Wark James M., Flip-chip on leads devices.
  22. Gademann Lothar,DEX ; Flohrs Peter,DEX ; Hartmann Juergen,DEX, Hybrid circuit with an electrically conductive adhesive.
  23. Laub Michael Frederick, Integrated circuit socket for ball grid array and land grid array lead styles.
  24. Farnworth Warren M., Mask repattern process.
  25. Farnworth Warren M., Mask repattern process.
  26. Akram Salman, Method and apparatus for packaging flip chip bare die on printed circuit boards.
  27. Hembree David R. ; Farnworth Warren M. ; Wood Alan G., Method and apparatus for testing an unpackaged semiconductor die.
  28. Akram Salman, Method for fabricating microbump interconnect for bare semiconductor dice.
  29. Akram Salman, Method for fabricating microbump interconnect for bare semiconductor dice.
  30. Stansbury Darryl M., Method for forming bumps on a semiconductor die using applied voltage pulses to an aluminum wire.
  31. Aulicino Anthony M. (North York CAX) Lyn Robert J. (Richmond Hill CAX), Method for forming solder balls on a substrate.
  32. Akram Salman ; Brooks Jerry M., Method of constructing stacked packages.
  33. Akram Salman ; Brooks Jerry M., Method of constructing stacked packages.
  34. Wark James M., Method of fabricating flip-chip on leads devices and resulting assemblies.
  35. Danner Paul A. (Beaverton OR), Method of fabricating solder ball array.
  36. Akram Salman, Method of forming conductive bumps on die for flip chip applications.
  37. Buchoff Leonard S. (Bloomfield NJ) Kosiarski Joseph P. (Englishtown NJ) Dalamangas Chris A. (Union NJ), Method of making electrically conductive connector.
  38. Akram Salman (Boise ID) Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID), Method of producing a single piece package for semiconductor die.
  39. Lin Paul T. (Austin TX), Method of transferring solder balls onto a semiconductor device.
  40. Distefano Thomas H. ; Fjelstad Joseph, Methods for providing void-free layers for semiconductor assemblies.
  41. Akram Salman, Microbump interconnect for bore semiconductor dice.
  42. Akram Salman ; Hembree David R. ; Farnworth Warren M., Micromachined chip scale package.
  43. Love David G. (Pleasanton CA), Module test card.
  44. Hsuan Min-Chih,TWX ; Lin Cheng-Te,TWX, Multi-chip chip scale package.
  45. Reid Gilbert R. (Norristown PA), Multiple solder pre-form with non-fusible web.
  46. Hayes Donald J., Process for manufacturing metal ball electrodes for a semiconductor device.
  47. Wood Alan G. ; Farnworth Warren M., Process for packaging a semiconductor die using dicing and testing.
  48. Miguel Albert Capote ; Xiaoqi Zhu ; Robert Vinson Burress ; Yong-Joon Lee, Semiconductor flip-chip package and method for the fabrication thereof.
  49. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Single piece package for semiconductor die.
  50. Noel Raymond (Menlo Park CA) Robinson William M. (Palo Alto CA) Cherian Gabe (Fremont CA) Clifford Thomas H. (Half Moon Bay CA) Carlomagno William D. (Redwood City CA) Deasy William M. (Redwood City , Solder delivery systems.
  51. Dyce John W. (Sidney NY) Buczak Ronald F. (Poughkeepsie NY), Solder pack and method of manufacture thereof.
  52. Park Sang Wook,KRX ; Cho Soon Jin,KRX, Stack package and method of fabricating the same.
  53. Akram Salman, Stacked leads-over chip multi-chip module.
  54. Akram Salman, Stacked leads-over-chip multi-chip module.
  55. Farnworth Warren M., Surface mount IC using silicon vias in an area array format or same size as die array.
  56. Hembree David R. (Boise ID) Farnworth Warren M. (Nampa ID), Temporary connection of semiconductor die using optical alignment techniques.
  57. Wark James M. ; Akram Salman, Thin film capacitor coupons for memory modules and multi-chip modules.
  58. Akram Salman ; Farnworth Warren M., Use of nitrides for flip-chip encapsulation.
  59. Duesman Kevin G. ; Farnworth Warren M., Utilization of die repattern layers for die internal connections.

이 특허를 인용한 특허 (36)

  1. Boon,Suan Jeung; Chia,Yong Poo; Eng,Meow Koon; Low,Siu Waf, Castellated chip-scale packages and methods for fabricating the same.
  2. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Chip package.
  3. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  4. Doan, Trung T., Die-wafer package and method of fabricating same.
  5. Hacke, Hans-J?rgen; Wossler, Manfred, Electronic chip component with an integrated circuit and fabrication method.
  6. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
  7. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  8. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
  9. Kilger, Thomas, Integrated system and method of making the integrated system.
  10. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  11. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Method of fabricating chip package.
  12. Kondo, Koichi, Method of processing wafer.
  13. Mostafazadeh,Shahram; Smith,Joseph O., Multichip packages with exposed dice.
  14. Meyer, Thorsten; Brunnbauer, Markus; Pohl, Jens, Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device.
  15. Boon, Suan Jeung; Chia, Yong Poo; Eng, Meow Koon; Low, Siu Waf, Semiconductor device assemblies and packages.
  16. Boon, Suan Jeung; Chia, Yong Poo; Eng, Meow Koon; Low, Siu Waf, Semiconductor device assemblies and packages with edge contacts and sacrificial substrates and other intermediate structures used or formed in fabricating the assemblies or packages.
  17. Poo,Chia Yong; Jeung,Boon Suan; Kwang,Chua Swee; Waf,Low Siu; Yu,Chan Min; Loo,Neo Yong, Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assemblies and packages including such semiconductor devices or packages and associated meth.
  18. Poo,Chia Yong; Jeung,Boon Suan; Waf,Low Siu; Yu,Chan Min; Loo,Neo Yong; Kwang,Chua Swee, Semiconductor devices including peripherally located bond pads, intermediates thereof, assemblies, and packages including the semiconductor devices, and support elements for the semiconductor devices.
  19. Chang, Hong-Da; Liao, Hsin-Yi, Semiconductor package and method of fabricating the same.
  20. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
  21. Kim, Soonbum, Semiconductor package, method of fabricating the same, and semiconductor module.
  22. Holland, Andrew G., Semiconductor packages.
  23. Yoshida, Akito; Heo, Young Wook, Stackable semiconductor package.
  24. Yoshida, Akito; Heo, Young Wook, Stackable semiconductor package.
  25. Yu, Chen-Hua; Liu, Chung-Shi; Kuo, Hung-Jui, Staggered via redistribution layer (RDL) for a package and a method for forming the same.
  26. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
  27. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
  28. Chia, Yong Poo; Boon, Suan Jeung; Low, Siu Waf; Neo, Yong Loo; Ser, Bok Leng, Super high density module with integrated wafer level packages.
  29. Chia, Yong Poo; Boon, Suan Jeung; Low, Siu Waf; Neo, Yong Loo; Ser, Bok Leng, Super high-density module with integrated wafer level packages.
  30. Chia, Yong Poo; Boon, Suan Jeung; Low, Siu Waf; Neo, Yong Loo; Ser, Bok Leng, Super high-density module with integrated wafer level packages.
  31. Poo,Chia Yong; Jeung,Boon Suan; Waf,Low Siu; Yu,Chan Min; Loo,Neo Yong; Kwang,Chua Swee, Support elements for semiconductor devices with peripherally located bond pads.
  32. Nguyen,Luu Thanh; Pham,Ken; Deane,Peter; Mazotti,William Paul; Roberts,Bruce Carlton; Liu,Jia, Techniques for joining an opto-electronic module to a semiconductor package.
  33. Nguyen,Luu Thanh; Pham,Ken; Deane,Peter; Mazotti,William Paul; Roberts,Bruce Carlton; Liu,Jia, Techniques for joining an opto-electronic module to a semiconductor package.
  34. Boon, Suan Jeung, Wafer level pre-packaged flip chip.
  35. Boon, Suan Jeung, Wafer level pre-packaged flip chip system.
  36. Boon, Suan Jeung, Wafer level pre-packaged flip chip systems.
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