Process for producing semiconductor article using graded epitaxial growth
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/00
출원번호
US-0379355
(2003-03-04)
발명자
/ 주소
Cheng, Zhi-Yuan
Fitzgerald, Eugene A.
Antoniadis, Dimitri A.
Hoyt, Judy L.
출원인 / 주소
Masachusetts Institute of Technology
대리인 / 주소
Testa, Hurwitz & Thibeault, LLP
인용정보
피인용 횟수 :
70인용 특허 :
118
초록▼
A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex(x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGeylayer, a thin strained Si1-zGezlayer and another relaxed Si1-yGeylayer. Hydrogen
A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex(x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGeylayer, a thin strained Si1-zGezlayer and another relaxed Si1-yGeylayer. Hydrogen ions are then introduced into the strained SizGezlayer. The relaxed Si1-yGeylayer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGeylayer remains on the second substrate. In another exemplary embodiment, a graded Si1-xGexis deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.
대표청구항▼
1. A method for forming a semiconductor layer, the method comprising: forming a first heterostructure by: forming a graded Si1-xGexbuffer layer on a first substrate, the graded Si1-xGexbuffer layer having a Ge concentration x increasing from zero to a value y; forming a relaxed Si1-yGeylayer o
1. A method for forming a semiconductor layer, the method comprising: forming a first heterostructure by: forming a graded Si1-xGexbuffer layer on a first substrate, the graded Si1-xGexbuffer layer having a Ge concentration x increasing from zero to a value y; forming a relaxed Si1-yGeylayer on the graded Si1-xGexbuffer layer; forming a separation layer on the relaxed Si1-yGeylayer; and forming a second relaxed layer over the separation layer; bonding the first heterostructure to a second substrate to define a second heterostructure; and splitting the second heterostructure along the separation layer, wherein the second relaxed layer remains on the second substrate after the second heterostructure is split. 2. The method of claim 1, wherein at least one of the relaxed layer and the separation layer comprises at least one material selected from the group consisting of Si1-wGew,Ge, GaAs, AlAs, ZnSe and InGaP. 3. The method of claim 1, further comprising: forming at least one of a device layer and a device, after the step of forming the second relaxed layer. 4. The method of claim 1, further comprising: planarizing the second relaxed layer before bonding the first heterostructure to the second substrate. 5. The method of claim 1, further comprising: cleaning at least one of the first heterostructure and the second substrate before the step of bonding. 6. The method of claim 1, wherein splitting the second heterostructure comprises annealing. 7. The method of claim 1, further comprising: removing at least one of (i) a remaining portion of the separation layer, and (ii) a top portion of the second relaxed layer from the second substrate after the step of splitting. 8. The method of claim 1, further comprising: forming at least one of a device layer and a device after the step of splitting. 9. The method of claim 1, further comprising: after splitting the second heterostructure along the separation layer, planarizing a portion of the first heterostructure split from the second substrate; and forming new layers on the remaining first heterostructure portion. 10. The method of claim 1 wherein the separation layer comprises a strained layer. 11. The method of claim 1, further comprising: introducing ions into the separation layer, prior to bonding the first heterostructure to the second substrate. 12. The method of claim 1 wherein the separation layer comprises a defect layer. 13. The method of claim 1 wherein the second substrate comprises silicon. 14. The method of claim 1 wherein the second substrate comprises an insulator layer. 15. The method of claim 1 wherein bonding the first heterostructure to the second substrate comprises bonding to the insulator layer. 16. The method of claim 10, wherein the strained layer comprises at least one of Si1-zGezwith z≠y and a III-V material. 17. The method of claim 11, further comprising: forming an insulating layer before the step of introducing ions. 18. The method of claim 11, further comprising: planarizing the second relaxed layer before the step of introducing ions. 19. The method of claim 11, wherein the ions comprise at least one of hydrogen H+ions and H2+ions.
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Godbey David J. (Bethesda MD) Hughes Harold L. (West River MD) Kub Francis J. (Severna Park MD), Method of producing a thin silicon-on-insulator layer.
Dmbkes Heinrich (Ulm DEX) Herzog Hans-J. (Neu-Ulm DEX) Jorke Helmut (Gerstetten DEX), Modulation doped field effect transistor with doped SixGe1-x-intrinsic Si layering.
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Kamins Theodore I. (Palo Alto) Noble David B. (Sunnyvale) Hoyt Judy L. (Palo Alto) Gibbons James F. (Palo Alto) Scott Martin P. (San Francisco CA), Selective and non-selective deposition of Si1-xGex on a Si subsrate that is partially maske.
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