초록 ▼

A system for multi-carrier transmission which can secure the transmission capacity under the noise environment whose noise changes cyclically is provided. A mapping section in an ATU-C (ADSL transceiver unit, central office end) memorizes the bit allocation allocating to each carrier and transmissio

A system for multi-carrier transmission which can secure the transmission capacity under the noise environment whose noise changes cyclically is provided. A mapping section in an ATU-C (ADSL transceiver unit, central office end) memorizes the bit allocation allocating to each carrier and transmission power allocation using for each carrier at the period that the noise generated at the data transmission to a downstream direction is large and the bit allocation allocating to each carrier and transmission power allocation using for each carrier at the period that the noise generated at the data transmission to an upstream direction is large. And a demapping section in an ATU-R (ADSL transceiver unit, remote terminal end) also memorizes the memorized bit allocation and transmission power allocation. At the time of the data transmission to the downstream direction, the bit allocation and transmission power allocation is allocated to each carrier of the high frequency band, by making the bit rate at the period that the noise generated at the data transmission to the downstream direction is small higher than the bit rate at the period that the noise is large. With this, the transmission capacity to the downstream direction can be secured.

대표청구항 ▼

A system for multi-carrier transmission which can secure the transmission capacity under the noise environment whose noise changes cyclically is provided. A mapping section in an ATU-C (ADSL transceiver unit, central office end) memorizes the bit allocation allocating to each carrier and transmissio

A system for multi-carrier transmission which can secure the transmission capacity under the noise environment whose noise changes cyclically is provided. A mapping section in an ATU-C (ADSL transceiver unit, central office end) memorizes the bit allocation allocating to each carrier and transmission power allocation using for each carrier at the period that the noise generated at the data transmission to a downstream direction is large and the bit allocation allocating to each carrier and transmission power allocation using for each carrier at the period that the noise generated at the data transmission to an upstream direction is large. And a demapping section in an ATU-R (ADSL transceiver unit, remote terminal end) also memorizes the memorized bit allocation and transmission power allocation. At the time of the data transmission to the downstream direction, the bit allocation and transmission power allocation is allocated to each carrier of the high frequency band, by making the bit rate at the period that the noise generated at the data transmission to the downstream direction is small higher than the bit rate at the period that the noise is large. With this, the transmission capacity to the downstream direction can be secured. path for the memory device to generate a decoded memory address; a counter connected to the decoder for counting the decoded memory address to generate a count; and a plurality of write drivers connected to the counter, wherein the counter is configured to activate at least one of the write drivers during the setup time. 10. The memory device of claim 9, wherein the memory device is configured to activate one-fourth of the write drivers simultaneously to access memory cells of the memory device. 11. The memory device of claim 9, wherein the memory device is configured to activate one-half of the write drivers simultaneously to access memory cells of the memory device. 12. The memory device of claim 9, wherein the memory device is configured to activate all of the write drivers simultaneously to access memory cells of the memory device. 13. A memory device comprising: a decoder for decoding at least a portion of a column address to generate a decoded address; a multiple bit shift register connected to the decoder for generating a count value based on the decoded address; and a number of write drivers connected to the multiple bit shift register for receiving the count value, wherein the multiple shift register is configured to activate at least one of the write drivers based on the count value during a memory access operation of the memory device. 14. The memory device of claim 13, wherein the decoder is configured to decode the portion of the column address during a setup time of a load path of the memory device, and the multiple bit shift register is configured to generate the count value during the setup time of the load path of the memory device. 15. The memory device of claim 13, wherein the decoder is configured to decode the portion of the column address at a first time, and the multiple shift register is configured to generate the count value at a second time later than the first time. 16. The memory device of claim 13 further comprising a multiplexer connected to the counter for determining a completion of a counting by the counter based on selected portion of the count value and the column address. 17. The memory device of claim 13, wherein the memory device is configured to activate one-fourth of the write drivers simultaneously to access memory cells of the memory device. 18. The memory device of claim 13, wherein the memory device is configured to activate one-half of the write drivers simultaneously to access memory cells of the memory device. 19. The memory device of claim 13, wherein the memory device is configured to activate all of the write drivers simultaneously to access memory cells of the memory device. 20. A memory device comprising: an input buffer for receiving a column address; a decoder connected to the input buffer for decoding a portion of the column address to generate a decoded address; a counter connected to the decoder for generating a count value based on the decoded address; a number of write drivers connected to the counter for receiving the count value; a column decoder connected to the counter for receiving the column address; and a memory array connected to the column decoder and the write drivers for receiving data from at least one of the write drivers based on the count value and the column address, wherein the decoder is configured to decode the portion of the column address before the column address is loaded into the column decoder. 21. The memory device of claim 20 further comprising a multiplexer connected to the counter for determining a completion of a counting by the counter based on selected portion of the count value and the column address. 22. The memory device of claim 20, wherein the memory device is configured to activate one-fourth of the write drivers simultaneously to access memory cells of the memory device. 23. The memory device of claim 20, wherein the memory device is configured to activate one-half of the write drivers simultaneously to acces s memory cells of the memory device. 24. The memory device of claim 20, wherein the memory device is configured to activate all of the write drivers simultaneously to access memory cells of the memory device. 25. A memory device comprising: an input buffer for receiving a memory address; a decoder connected to the input buffer for decoding a portion of the memory address to generate a decoded address; a counter connected to the decoder for generating a count value based on the decoded address, wherein the decoder is configured to generate the decoded address before the memory address is located into the counter; a holding circuit connected to the input buffer for holding an encoded version of the address; a multiplexor connected to the counter and the holding circuit for receiving the count value and the encoded version of the memory address to determine a completion of a counting by the counter; a number of write drivers connected to the counter for receiving the count value; and a memory array connected to the write drivers, wherein the counter is configured to activate at least one of the write drivers during a memory access operation of the memory device, and the decoder is configured to generate the decoded memory address before the memory address is loaded into the counter. 26. The memory device of claim 25, wherein the encoded version of the memory address includes at multiple bits and the decoded address includes multiple bits. 27. A system comprising: a processing unit; and a memory device connected to the processing unit, the memory device comprising: an input buffer for receiving a memory address; a decoder connected to the input buffer for generating a decoded memory address based on the memory address; and a counter connected to the decoder for generating a count value based on the decoded memory address, wherein the decoder is configured to decode the memory address before the memory address is loaded into the counter. 28. The system of claim 27, wherein the memory device further comprising a plurality of write drivers connected to the counter, wherein the counter is configured to activate one or more of the write drivers based on the count value during a memory access operation of the memory device. 29. The system of claim 27, wherein the memory device further comprising a multiplexer connected to the counter for determining a completion of a counting by the counter based on selected portion of the count value and the memory address. 30. The system of claim 27, wherein the memory device wherein the memory address is a column address of the memory device. 31. A system comprising: a processing unit; and a dynamic memory device connected to the processing unit, the dynamic memory device comprising: an input buffer for receiving a column address; a decoder connected to the input buffer for decoding a portion of the column address to generate a decoded address; a counter connected to the decoder for generating a count value based on the decoded address; a number of write drivers connected to the counter for receiving the count value; a column decoder connected to the counter for receiving the column address; and a memory array connected to the column decoder and the write drivers for receiving data from at least one of the write drivers based on the count value and the column address, wherein the decoder is configured to decode the portion of the column address before the column address is loaded into the column decoder. 32. The system of claim 31, wherein the memory device further comprising a multiplexer connected to the counter for determining a completion of a counting by the counter based on selected portion of the count value and the column address. 33. The system of claim 31, wherein the memory device is configured to activate one-fourth of the write drivers simultaneously to access memory cells of the memory device. 34. The system of claim 31, wherein the memory device is c onfigured to activate one-half of the write drivers simultaneously to access memory cells of the memory device. 35. The system of claim 31, wherein the memory device is configured to activate all of the write drivers simultaneously to access memory cells of the memory device. 36. A method of operating a memory device, the method comprising: receiving a memory address; decoding the memory address to produce decoded memory address; producing a count value based on the decoded memory address; and activating at least one write driver among a plurality of write drivers based on the count value during a setup time of a load path of the memory device. 37. The method of claim 36, wherein receiving a memory address includes receiving a column address. 38. The method of claim 36, wherein decoding the memory address includes decoding a portion of the memory address that controls write drivers and sense amplifiers of the memory device. 39. The method of claim 36, wherein decoding the memory address includes decoding at least two bits of the memory address. 40. The method of claim 36, wherein decoding the memory address occurs before the memory address is loaded into a column decoder. 41. The method of claim 36, wherein activating at least one write driver among a plurality of write drivers includes activating one-fourth of the write drivers. 42. The method of claim 36, wherein activating at least one write driver among a plurality of write drivers includes activating one-half of the write drivers. 43. The method of claim 36, wherein activating at least one write driver among a plurality of write drivers includes activating all of the write drivers. 99/064626, WO; WO99/065945, WO; 0000808, WO; WO00/004372, WO; WO00/004382, WO; WO00/004389, WO; WO00/006771, WO; WO00/011223, WO; WO00/014197, WO; WO00/040942, WO; WO00/043539, WO; WO00/053625, WO; WO00/053736, WO; WO00/053739, WO; WO00/065097, WO; WO00/065098, WO; WO00/073504, WO; WO01/116376, WO