최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0386431 (1999-08-31) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 324 인용 특허 : 117 |
A system and method, are provided for structuring batch activities for simplified reconfiguration. A series of processing steps is prepared for performing on input objects being streamed into a batch processing system. Each of the processing steps is encapsulated within at least one of a plurality o
A system and method, are provided for structuring batch activities for simplified reconfiguration. A series of processing steps is prepared for performing on input objects being streamed into a batch processing system. Each of the processing steps is encapsulated within at least one of a plurality of filters. The input objects are received and processed in the filters. Results are delivered from the filters incrementally during the processing of the input objects for reducing latency and enabling parallel processing. Connectors are utilized for connecting at least two of the plurality of filters each having a processing step for creating a process. One of the two filters is an input filter of the process and the other of the two filters is an output filter of the process. Connectors are also used for connecting input and output filters of different processes for forming a scalable system.
A system and method, are provided for structuring batch activities for simplified reconfiguration. A series of processing steps is prepared for performing on input objects being streamed into a batch processing system. Each of the processing steps is encapsulated within at least one of a plurality o
A system and method, are provided for structuring batch activities for simplified reconfiguration. A series of processing steps is prepared for performing on input objects being streamed into a batch processing system. Each of the processing steps is encapsulated within at least one of a plurality of filters. The input objects are received and processed in the filters. Results are delivered from the filters incrementally during the processing of the input objects for reducing latency and enabling parallel processing. Connectors are utilized for connecting at least two of the plurality of filters each having a processing step for creating a process. One of the two filters is an input filter of the process and the other of the two filters is an output filter of the process. Connectors are also used for connecting input and output filters of different processes for forming a scalable system. econd operating mode. 2. The semiconductor device as claimed in claim 1, wherein: the output control circuit outputs the first data through the nth data in synchronism with first through nth timing signals in the first operating mode; and the output control circuit outputs the (n+1)th data in synchronism with the second through nth timing signals in the second operating mode. 3. The semiconductor device as claimed in claim 2, wherein the first operating mode is a normal mode and the second operating mode is a test mode. 4. The semiconductor device as claimed in claim 1, wherein the first operating mode is a normal mode and the second operating mode is a test mode. 5. The semiconductor device as claimed in claim 1, wherein: the first data through the nth data are data read from a memory cell area; and the (n+1)th data is test data generated from an area other than the memory cell area. 6. A semiconductor device comprising: first through nth paths (where n is an integer greater than or equal to 2) to which first data through nth data are respectively applied; and a data output circuit converting the first data through the nth data into serial data in which the first data through the nth data are serially arranged in this order in a first operating mode, and having an (n+1)th input path via which (n+t)th data to be output to an outside of the semiconductor device are received said (n+1)th input path being connected to one of the second through nth paths so that the (n+1)th data on the (n+1) input path are output via one of the second through nth paths, without using the first path, in a second operating mode.
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