IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0081198
(2002-02-21)
|
발명자
/ 주소 |
|
출원인 / 주소 |
- Tyco Electronics Corporation
|
인용정보 |
피인용 횟수 :
19 인용 특허 :
22 |
초록
▼
An electrical connector assembly is provided including a CPA, a first connector housing, a second connector housing, a retention assembly, and a CPA mounting assembly. The CPA includes a retention assembly biasing element. A retention assembly is mounted to at least one of the first and second conne
An electrical connector assembly is provided including a CPA, a first connector housing, a second connector housing, a retention assembly, and a CPA mounting assembly. The CPA includes a retention assembly biasing element. A retention assembly is mounted to at least one of the first and second connector housings to maintain the first and second connector housings in contact when they are mated. The retention assembly includes a removal element, and is movable between a locked and unlocked position responsive to contact between the retention assembly biasing element of the CPA and the removal element. At least one of the first and second connector housings has a CPA mounting assembly mounted thereto. The CPA is slidably mounted to the CPA mounting assembly and is movable to first, second, and third positions. In its first position, the CPA permits engagement of the first and second connector housings. In its second position, the CPA prevents engagement and disengagement of the first and second connector housings. In its third position, the CPA biases at least a part of the retention assembly and permits disengagement of the first and second connector housings.
대표청구항
▼
An electrical connector assembly is provided including a CPA, a first connector housing, a second connector housing, a retention assembly, and a CPA mounting assembly. The CPA includes a retention assembly biasing element. A retention assembly is mounted to at least one of the first and second conne
An electrical connector assembly is provided including a CPA, a first connector housing, a second connector housing, a retention assembly, and a CPA mounting assembly. The CPA includes a retention assembly biasing element. A retention assembly is mounted to at least one of the first and second connector housings to maintain the first and second connector housings in contact when they are mated. The retention assembly includes a removal element, and is movable between a locked and unlocked position responsive to contact between the retention assembly biasing element of the CPA and the removal element. At least one of the first and second connector housings has a CPA mounting assembly mounted thereto. The CPA is slidably mounted to the CPA mounting assembly and is movable to first, second, and third positions. In its first position, the CPA permits engagement of the first and second connector housings. In its second position, the CPA prevents engagement and disengagement of the first and second connector housings. In its third position, the CPA biases at least a part of the retention assembly and permits disengagement of the first and second connector housings. 1. A method of making a microelectronic device comprising: forming a first layer over a substrate; removing portions of the first layer to expose a portion of the substrate and form substantially vertical sidewalls; forming a first spacer adjacent the sidewalls; forming a second spacer adjacent the first spacer; with the first and second spacers present, etching a recess into the substrate between the spacers, wherein the recess is the first structure formed beneath a surface of the substrate between the spacers; removing the second spacer; forming a dielectric layer superjacent the exposed portions of the substrate; forming an electrode superjacent the dielectric layer; and removing the first layer. 2. The method of claim 1, wherein etching a portion of the exposed substrate comprises isotropically etching the substrate. 3. The method of claim 1, wherein etching a portion of the exposed substrate comprises an isotropically etching the substrate. 4. The method of claim 1, further comprising oxidizing the exposed portions of the substrate, and wherein the etching a portion of the exposed substrate comprises etching the oxidized portions of the substrate. 5. A method of forming a field effect transistor, comprising: depositing an etch stop layer and a damascene layer over a silicon substrate; removing portions of the damascene and etch stop layers to expose portions of the silicon, and form sidewalls in the damascene and etch stop layers; forming a first spacer layer along the sidewalls of the damascene layer and the etch stop layer; forming a second spacer adjacent the first spacer; with the first and second spacers present, etching a recess into the substrate between the spacers, wherein the recess is the first structure formed beneath a surface of the substrate between the spacers; removing the second spacer; forming a gate dielectric layer superjacent the etched silicon; and depositing a gate electrode layer over the damascene and gate dielectric layers; planarizing the gate electrode layer so as to form a gate electrode; removing the damascene layer and etch stop layer; and forming source/drain terminals self-aligned to the gate electrode. 6. The method of claim 5, wherein planarizing the gate electrode layer comprises chemical mechanical polishing using the damascene layer as a polish stop. 7. The method of claim 5, further comprising implanting ions into the silicon substrate. 8. The method of claim 5, further comprising implanting ions into the silicon substrate, after the first and second spacers are formed. 9. The method of claim 5, further comprising performing a channel implant into the silicon using the damascene, first spacer, and second spacer layers as implant masks. 10. The method of claim 5 wherein forming source/drain terminals comprises implanting ions of a first conductivity type into the silicon, adjacent to the gate electrode; forming third spacers adjacent to the gate electrode, and implanting ions of a first conductivity type into the silicon, adjacent to the third spacers. 11. The method of claim 5, wherein etching the silicon comprises an isotropic etch. 12. A method of forming a field effect transistor, comprising: depositing an etch stop layer and a damascene layer over a silicon substrate; removing portions of the damascene and etch stop layers to expose portions of the silicon, and form sidewalls in the damascene and etch stop layers; forming a first spacer layer along the sidewalls of the damascene layer and the etch stop layer, and a second spacer adjacent the first spacer layer; with the first and second spacers present, etching a recess into the substrate between the spacers, wherein the recess is the first structure formed beneath a surface of the substrate between the spacers; removing the second spacer; forming a gate dielectric layer superjacent to the etched silicon; depositing a gate electrode layer over the damascene and gate dielectric layers; plana
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