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Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0233430 (2002-09-04)
우선권정보 JP-0226876 (1999-08-10)
발명자 / 주소
  • Noguchi, Junji
  • Ohashi, Naofumi
  • Takeda, Kenichi
  • Saito, Tatsuyuki
  • Yamaguchi, Hizuru
  • Owada, Nobuo
출원인 / 주소
  • Renesas Technology Corporation
대리인 / 주소
    Miles & Stockbridge P.C.
인용정보 피인용 횟수 : 5  인용 특허 : 33

초록

After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, with

대표청구항

After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, with

이 특허에 인용된 특허 (33)

  1. Islam Rabiul ; Gelatos Avgerinos V. ; Lucas Kevin ; Filipiak Stanley M. ; Venkatraman Ramnath, Copper interconnect structure and method of formation.
  2. Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
  3. Edelstein Daniel C. ; Horkans Wilma J. ; Luce Stephen E. ; Lustig Naftali E. ; Pope Keith R. ; Roper Peter D., Elimination of photo-induced electrochemical dissolution in chemical mechanical polishing.
  4. Teong Su-Ping (Singapore SGX), Etch stop for copper damascene process.
  5. Wang Pin-Chin C. ; You Lu, Forming and filling a recess in interconnect for encapsulation to minimize electromigration.
  6. Vines Landon B. ; Bellows Craig A. ; Parmantie Walter D., IC interconnect formation with chemical-mechanical polishing and silica etching with solution of nitric and hydrofluoric acids.
  7. Cronin John Edward, Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same.
  8. Maekawa Kazuyoshi,JPX, Manufacturing method of semiconductor device having high pressure reflow process.
  9. Judy H. Huang ; Christopher Dennis Bencher ; Sudha Rathi ; Christopher S. Ngai ; Bok Hoen Kim, Method and apparatus for reducing copper oxidation and contamination in a semiconductor device.
  10. Filipiak Stanley M. (Pflugerville TX) Gelatos Avgerinos (Austin TX), Method for capping copper in semiconductor devices.
  11. Cunningham, James A., Method for making integrated circuit including interconnects with enhanced electromigration resistance.
  12. Homma Yoshio,JPX ; Kondo Seiichi,JPX ; Sakuma Noriyuki,JPX ; Ohashi Naofumi,JPX ; Imai Toshinori,JPX ; Yamaguchi Hizuru,JPX ; Owada Nobuo,JPX, Method for manufacturing a semiconductor device.
  13. Imai, Toshinori; Ohashi, Naofumi; Homma, Yoshio; Kondo, Seiichi, Method for manufacturing a semiconductor device.
  14. Matsui Masaki,JPX ; Yamauchi Shoichi,JPX ; Ohshima Hisayoshi,JPX ; Onoda Kunihiro,JPX ; Asai Akiyoshi,JPX ; Sasaya Takanari,JPX ; Enya Takeshi,JPX ; Sakakibara Jun,JPX, Method for manufacturing a semiconductor substrate.
  15. Nogami Takeshi ; Chan Simon, Method for reducing electromigration in a copper interconnect.
  16. Venkatraman Ramnath (Austin TX), Method of alloying an interconnect structure with copper.
  17. Venkatraman Ramnath ; Weitzman Elizabeth J. ; Fiordalice Robert W., Method of forming an interconnect structure.
  18. Nogami Takeshi ; Lopatin Sergey ; Joo Young-Chang, Method of forming copper/copper alloy interconnection with reduced electromigration.
  19. Van Ngo Minh ; Cheung Robin W., Method of forming high density capping layers for copper interconnects with improved adhesion.
  20. Takashi Kawanoue JP; Tetsuo Matsuda JP; Hisashi Kaneko JP; Tadashi Iijima JP, Method of manufacturing a copper interconnect.
  21. Chan Lap ; Zheng Jia Zhen,SGX, Method of manufacturing copper interconnect with top barrier layer.
  22. Hoshino Kazuhiro (Tokyo JPX), Method of producing semiconductor device.
  23. Pramanick Shekhar ; Nogami Takeshi ; Ngo Minh Van, Method of reliably capping copper interconnects.
  24. Lai Jane-Bai,TWX ; Liu Chung-Shi,TWX ; Bao Tien-I,TWX ; Jang Syun-Ming,TWX ; Chang Chung-Long,TWX ; Wang Hui-Ling,TWX ; Wu Szu-An,TWX ; Cheng Wen-Kung,TWX ; Tsan Chun-Ching,TWX ; Wang Ying-Lang,TWX, Methods to improve copper-fluorinated silica glass interconnects.
  25. Donnelly ; Jr. Vincent Michael ; Ueno Kazuyoshi,JPX, Multilevel wiring structure and method of fabricating a multilevel wiring structure.
  26. Watanabe Jinzo,JPX ; Yamashita Takeo,JPX ; Nakamura Masakazu,JPX ; Aoyama Shintaro,JPX ; Wakamatsu Hidetoshi,JPX ; Shibata Tadashi,JPX ; Ohmi Tadahiro,JPX ; Konishi Nobuhiro,JPX ; Morita Mizuho,JPX ;, Oxide film forming method.
  27. Kondo Seiichi,JPX ; Homma Yoshio,JPX ; Sakuma Noriyuki,JPX ; Takeda Kenichi,JPX ; Hinode Kenji,JPX, Polishing method.
  28. Gelatos Avgerinos V. (Austin TX) Fiordalice Robert W. (Austin TX), Process for forming copper interconnect structure.
  29. Kadomura Shingo (Kanagawa JPX), Process for forming copper wiring.
  30. Naofumi Ohashi JP; Junji Noguchi JP; Toshinori Imai JP; Hizuru Yamaguchi JP; Nobuo Owada JP; Kenji Hinode JP; Yoshio Homma JP; Seiichi Kondo JP, Process for manufacturing semiconductor integrated circuit device.
  31. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Robust post Cu-CMP IMD process.
  32. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.
  33. Pasch Nicholas F., Use of corrosion inhibiting compounds to inhibit corrosion of metal plugs in chemical-mechanical polishing.

이 특허를 인용한 특허 (5)

  1. Sakata,Toyokazu, Etching method and semiconductor device fabricating method.
  2. Ohtorii,Hiizu; Tai,Kaori; Horikoshi,Hiroshi; Komai,Naoki; Sato,Shuzo, Etching solution, etching method and method for manufacturing semiconductor device.
  3. Lin,Shih Chi; Wang,Francis; Lee,Wen Long; Wu,Sez An, Hillock reduction in copper films.
  4. Daubenspeck, Timothy H.; Landers, William F.; Zupanski-Nielsen, Donna S., Method for fabricating last level copper-to-C4 connection with interfacial cap structure.
  5. Kawanami, Koji; Tabuchi, Kiyotaka, Method for production of semiconductor devices.
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