$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Apparatus and method for fluid-based cooling of heat-generating devices 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/20
출원번호 US-0367740 (2003-02-19)
우선권정보 SG-200207020 (2002-11-21)
발명자 / 주소
  • Pinjala, Damaruganath
  • Kripesh, Vaidyanathan
  • Zhang, Hengyun
  • Iyer, Mahadevan K
  • Nagarajan, Ranganathan
출원인 / 주소
  • Institute of Microelectronics
대리인 / 주소
    Nath & Associates PLLC
인용정보 피인용 횟수 : 42  인용 특허 : 11

초록

Method and apparatus for fluid-based cooling of heat-generating devices are disclosed. A heat-generating device is mounted on a carrier. The heat-generating device is spatially displaced from the surface of the carrier, thereby forming a channel. The heat-generating device and the carrier are enclos

대표청구항

Method and apparatus for fluid-based cooling of heat-generating devices are disclosed. A heat-generating device is mounted on a carrier. The heat-generating device is spatially displaced from the surface of the carrier, thereby forming a channel. The heat-generating device and the carrier are enclos

이 특허에 인용된 특허 (11)

  1. Fuesser Hans-Juergen,DEX ; Zachai Reinhard,DEX ; Muench Wolfram,DEX ; Gutheit Tim,DEX, Arrangement of plural micro-cooling devices with electronic components.
  2. Hamilton Robin E. ; Fagan Thomas J. ; Kennedy Paul G. ; Woodward William S., Closed loop liquid cooling for semiconductor RF amplifier modules.
  3. Iversen Arthur H. (Saratoga CA), Cooling of large semi-conductor devices.
  4. Tustaniwskyj Jerry I. (Mission Viejo CA) Halkola Kyle G. (San Diego CA), Liquid cooled multi-chip integrated circuit module incorporating a seamless compliant member for leakproof operation.
  5. Frey Toni ; Stuck Alexander,CHX ; Zehringer Raymond,CHX, Liquid cooling device for a high-power semiconductor module.
  6. Loo Mike C. (San Jose CA) Vogel Marlin R. (Fremont CA), Multi-chip cooling module and method.
  7. Burhan Ozmat ; Mustansir Hussainy Kheraluwala ; Eladio Clemente Delgado ; Charles Steven Korman ; Paul Alan McConnelee, Power electronic module packaging.
  8. Mikubo, Kazuyuki; Kitajo, Sakae, Semiconductor device attaining both high speed processing and sufficient cooling capacity.
  9. Gates ; Jr. Louis E. (Westlake Village CA) Finnila Charles A. (Manhattan Beach CA), Stacked wafer electronic package.
  10. Parks Howard L. (Los Gatos CA), Three-dimensional microelectronic package for semiconductor chips.
  11. Moresco Larry L. (San Carlos CA) Horine David A. (Los Altos CA) Wang Wen-Chou V. (Cupertino CA), Three-dimensional multichip module.

이 특허를 인용한 특허 (42)

  1. Hsu, Louis L.; Ji, Brian L.; Liu, Fei; Murray, Conal E., Air channel interconnects for 3-D integration.
  2. Bernstein, Kerry; Brunschwiler, Thomas; Michel, Bruno, Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly.
  3. Bernstein, Kerry; Brunschwiler, Thomas; Michel, Bruno, Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly.
  4. Bernstein, Kerry; Brunschwiler, Thomas; Michel, Bruno, Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly.
  5. Bernstein, Kerry; Brunschwiler, Thomas; Michel, Bruno, Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly.
  6. Bernstein, Kerry; Brunschwiler, Thomas; Michel, Bruno, Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly.
  7. Bernstein, Kerry; Brunschwiler, Thomas; Michel, Bruno, Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly.
  8. Bernstein, Kerry; Brunschwiler, Thomas; Michel, Bruno, Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly.
  9. Teneketges, Nicholas J., Automated test equipment with DIB mounted three dimensional tester electronics bricks.
  10. Lin, Jing-Cheng; Tsai, Po-Hao, Bump structures for semiconductor package.
  11. Lin, Jing-Cheng; Tsai, Po-Hao, Bump structures for semiconductor package.
  12. Sakamoto, Hideyuki; Saito, Hidefumi; Koike, Yasuhiro; Tsukizawa, Masao, Circuit device.
  13. Sakamoto, Hideyuki; Saito, Hidefumi; Koike, Yasuhiro; Tsukizawa, Masao, Circuit device.
  14. Sakamoto, Hideyuki; Saito, Hidefumi; Koike, Yasuhiro; Tsukizawa, Masao, Circuit device and method of manufacturing the same.
  15. Sakamoto, Hideyuki; Saito, Hidefumi; Koike, Yasuhiro; Tsukizawa, Masao, Circuit device and method of manufacturing the same.
  16. Sakamoto, Hideyuki; Saito, Hidefumi; Koike, Yasuhiro; Tsukizawa, Masao, Circuit device, circuit module, and outdoor unit.
  17. Sakamoto, Hideyuki; Saito, Hidefumi; Koike, Yasuhiro; Tsukizawa, Masao, Circuit module.
  18. Murata, Takahito, Cooling apparatus.
  19. Heydari,Ali; Yang,Ji L., Direct contact cooling liquid embedded package for a central processor unit.
  20. Brunschwiler, Thomas J.; Linderman, Ryan J.; Michel, Bruno; Rothuizen, Hugo E., Integrated circuit stack.
  21. Brunschwiler, Thomas J.; Linderman, Ryan J.; Michel, Bruno; Rothuizen, Hugo E., Integrated circuit stack.
  22. Salmon,Peter C., Interconnection circuit and electronic module utilizing same.
  23. Myers, Bruce A.; Brauer, Eric A., Liquid cooled power electronic circuit comprising a stacked array of directly cooled semiconductor chips.
  24. Myers, Bruce A.; Ratell, Joseph M., Liquid cooled power electronic circuit comprising stacked direct die cooled packages.
  25. Lin, Jing-Cheng; Tsai, Po-Hao, Mechanisms for controlling bump height variation.
  26. Yazawa, Kazuaki; Bar-Cohen, Avram, Method and apparatus for converting dissipated heat to work energy.
  27. Lin, Jing-Cheng; Tsai, Po-Hao, Method of forming a plurality of bumps on a substrate and method of forming a chip package.
  28. Yean, Tay Wuu; Ai-Chie, Wang, Methods of forming and assembling pre-encapsulated assemblies and of forming associated semiconductor device packages.
  29. Breinlinger, Keith; Ostertag, Edward; Sartschev, Ronald A.; Teneketges, Nicholas J., Pin electronics liquid cooled multi-module for high performance, low cost automated test equipment.
  30. Lin, Jing-Cheng; Tsai, Po-Hao, Planarized bumps for underfill control.
  31. Anwar, Mohammad N; Desai, Prakash Haribhai; Gleason, Sean E; Welchko, Brian A, Prediction strategy for thermal management and protection of power electronic hardware.
  32. Salmon,Peter C., Repairable three-dimensional semiconductor subsystem.
  33. Salmon, Peter C., Scalable subsystem architecture having integrated cooling channels.
  34. Ellsberry,Mark; Schmitz,Charles E.; Chen,Chi She; Allison,Victor, Stackable electronic assembly.
  35. Hsiao, Yi-Li; Lin, Li-Yen; Tung, Chih-Hang, Stacked package and method of manufacturing the same.
  36. Vadhavkar, Sameer S.; Li, Xiao; Groothuis, Steven K.; Li, Jian; Gandhi, Jaspreet S.; Derderian, James M.; Hembree, David R., Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods.
  37. Vadhavkar, Sameer S.; Li, Xiao; Groothuis, Steven K.; Li, Jian; Gandhi, Jaspreet S.; Derderian, James M.; Hembree, David R., Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods.
  38. Vadhavkar, Sameer S.; Li, Xiao; Gandhi, Jaspreet S., Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems.
  39. Moshayedi,Mark, Systems and methods for stacking chip components.
  40. Yamaji,Yasuhiro, Three-dimensionally mounted semiconductor module and three-dimensionally mounted semiconductor system.
  41. Campbell, Levi A.; Chu, Richard C.; David, Milnes P.; Ellsworth, Jr., Michael J.; Iyengar, Madusudan K.; Simons, Robert E.; Singh, Prabjit, Two-phase, water-based immersion-cooling apparatus with passive deionization.
  42. Campbell, Levi A.; Chu, Richard C.; David, Milnes P.; Ellsworth, Michael J.; Iyengar, Madhusudan K.; Simons, Robert E.; Singh, Prabjit, Two-phase, water-based immersion-cooling apparatus with passive deionization.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로