IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0134090
(2002-04-25)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
0 인용 특허 :
10 |
초록
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An integrated circuit architecture having a common circuit including a system controller and a data bus coupled to a plurality of redundant processing units, or clusters, each adapted to perform self-diagnosis and to report a status thereof to the system controller via a status line. The system cont
An integrated circuit architecture having a common circuit including a system controller and a data bus coupled to a plurality of redundant processing units, or clusters, each adapted to perform self-diagnosis and to report a status thereof to the system controller via a status line. The system controller is adapted to disconnect a faulty or unresponsive cluster from the common circuit in order to allow normal operation of remaining operative components. By such means yield of the integrated circuit is increased as well as the reliability of a device containing the integrated circuit.
대표청구항
▼
An integrated circuit architecture having a common circuit including a system controller and a data bus coupled to a plurality of redundant processing units, or clusters, each adapted to perform self-diagnosis and to report a status thereof to the system controller via a status line. The system cont
An integrated circuit architecture having a common circuit including a system controller and a data bus coupled to a plurality of redundant processing units, or clusters, each adapted to perform self-diagnosis and to report a status thereof to the system controller via a status line. The system controller is adapted to disconnect a faulty or unresponsive cluster from the common circuit in order to allow normal operation of remaining operative components. By such means yield of the integrated circuit is increased as well as the reliability of a device containing the integrated circuit. ein the first, second, third, fourth, and fifth transistors comprise NMOS transistors. 7. The semiconductor memory device of claim 5, wherein the second and third control signals are complementary signals. 8. The semiconductor memory device of claim 5, wherein logic states of the second and third control signals are determined depending on data to be programmed during the program operation. 9. The semiconductor memory device of claim 5, wherein the second control signal is activated when the data on the sense node is transferred to the latch, and the third control signal is activated when the latch is set to a predetermined state and the data in the latch is transferred to the data bus. 10. The semiconductor memory device of claim 3, wherein the second transfer circuit includes first and second pull-up transistors serially coupled between a power supply voltage and the sense node and first and second pull-down transistors serially coupled between the sense node and a ground voltage; and wherein the first pull-up transistor and the second pull-down transistor are switched according to a logic state of the second latch node, the second pull-up transistor is switched according to a load control signal, and the first pull-up transistor is switched according to an inverted version of the load control signal. 11. The semiconductor memory device of claim 3, wherein the second sense and latch block includes: a second latch for holding data, the second latch having a third latch node and a fourth latch node; a third transfer circuit for transferring data on the data bus to the second latch during a program operation, the third transfer circuit being coupled to third and fourth latch nodes, the sense node, and the internal node; and a fourth transfer circuit for transferring data held in the latch to the sense node during the program operation, the fourth transfer circuit being coupled between the fourth latch node and the sense node; wherein the third latch node is structured to have data transferred from the data bus during the program operation, and the fourth transfer circuit is structured to pull up/down the sense node depending on a logic state of the second latch node. 12. The semiconductor memory device of claim 11, wherein the fourth transfer circuit is structured to transfer the data on the data bus to the second latch during the read operation, and is structured to transfer the data in the latch to the data bus via the switch circuit. 13. The semiconductor memory device of claim 3, wherein the third transfer circuit includes: a first transistor having a source coupled to the internal node, a gate coupled to a first control signal, and a drain; a second transistor having a source coupled to the drain of the first transistor, a drain coupled to the third latch node, and a gate coupled to a second control signal; a third transistor having a source coupled to the drain of the first transistor, a drain coupled to the fourth latch node, and a gate coupled to a third control signal; a fourth transistor having a drain coupled to the drain of the first transistor, a gate coupled to the sense node, and a source; and a fifth transistor having a drain coupled to the source of the fourth transistor, a source coupled to a ground voltage, and a gate coupled to a fourth control signal. 14. The semiconductor memory device of claim 13, wherein the first, second, third fourth and fifth transistors are NMOS transistors. 15. The semiconductor memory device of claim 13, wherein the second and third control signals are complementary signals. 16. The semiconductor memory device of claim 13, wherein logic states of the second and third control signals are determined depending on data to be programmed during the program operation. 17. The semiconductor memory device of claim 13, wherein the second control signal is structured to be activated when the data on the data bus is transferred to the latch, and the third control signal i
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