IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0502764
(2000-02-11)
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발명자
/ 주소 |
- O'Toole, James E.
- Tuttle, John R.
- Tuttle, Mark E.
- Lowrey, Tyler
- Devereaux, Kevin M.
- Pax, George E.
- Higgins, Brian P.
- Ovard, David K.
- Yu, Shu-Sun
- Rotzoll, Robert R.
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
36 인용 특허 :
125 |
초록
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A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receive
A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.
대표청구항
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A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receive
A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range. t one of the plurality of word lines in response to a clock. 19. The apparatus of claim 18, wherein the timing of the clock is adjustable. o a signal-to-noise ratio between the individual lines. 9. Circuit arrangement for reading out and for storing binary memory cell signals according to claim 4, wherein a section of at least one local data line pair extends over a length of at least one memory cell array. he top cell array unit disposed symmetrically about the sense amplifiers, and reference bit lines of the top cell array unit correspond to main bit lines of the bottom cell array unit disposed symmetrically about the sense amplifiers. 2. The nonvolatile ferroelectric memory device of claim 1, wherein the top and bottom cell array units are disposed in an open bit line structure, and each reference array unit comprising: a middle reference array unit disposed in a middle section of the cell array unit; and an edge reference array unit disposed at an edge section of the cell array unit. 3. The nonvolatile ferroelectric memory device of claim 2, wherein the sense amplifiers are disposed alternately to lie each between the top and bottom cell array units, or between the top cell array unit and the edge reference array unit, or between the bottom cell array unit and the edge reference array unit. 4. The nonvolatile ferroelectric memory device of claim 1, wherein the top and bottom cell array units are disposed in a folded bit line structure. 5. The nonvolatile ferroelectric memory device of claim 1, wherein the top and bottom cell array units are disposed in a folded bit line structure, and the bit lines connected to the sense amplifiers are disposed in an open bit line structure, wherein: each pair of consecutive bit lines from the top cell array unit shares one of the sense amplifiers, and each pair of consecutive the bit lines from the bottom cell array unit shares the same sense amplifier as the corresponding pair from the top cell array unit, whereby the nonvolatile ferroelectric memory device has a hybrid bit line structure. 6. The nonvolatile ferroelectric memory device of claim 5, wherein the bit lines of the top and bottom cell array units are connected to the sense amplifiers through a plurality of switching transistors, whereby the bit lines are respectively controlled by these transistors. 7. The nonvolatile ferroelectric memory device of claim 6, further comprising a main bit line switching signal applying line, wherein each of a plurality of the switching transistors has a gate terminal connected to the main bit line switching signal applying line, a drain terminal connected to a source of a preceding adjacent switching transistor, and a source terminal connected to a ground voltage terminal. 8. The nonvolatile ferroelectric memory device of claim 2, the plurality of sense amplifiers further comprising: a plurality of signal buses, each signal bus corresponding to one sense amplifier; a write control unit driven by a data transferred through a signal bus; a first switching transistor disposed between the signal bus and a power supply voltage terminal; a second switching transistor disposed between a reference bus and a ground voltage terminal; and a third switching transistor disposed between the reference bus and the power supply voltage terminal. 9. A nonvolatile ferroelectric memory device comprising: a top cell array unit including a plurality of unit cells; a bottom cell array unit including a plurality of unit cells; a middle reference array unit disposed in a middle area between the top and bottom cell array units; a plurality of edge reference array units disposed at edge sections of the top and bottom cell array units, respectively; and a plurality of sense amplifiers, wherein the top cell array unit is disposed at an upper section, the bottom cell array unit is disposed at a lower section, the top and bottom cell array units being disposed symmetrically about the sense amplifiers, wherein the sense amplifiers are disposed alternately to lie each between the top and bottom cell array units, or between the top cell array unit and an edge reference array unit, or between the bottom cell array unit and an edge reference array unit, wherein bit lines at the lower section below the sense amplifiers disposed between the top and bottom cell array units and the edge reference array u nits are main bit lines when the bit lines at the upper section above the sense amplifiers disposed between the top and bottom cell array units and the edge reference array units are reference bit lines, and wherein the bit lines at the lower section below the sense amplifiers formed between the top and bottom cell array units and the edge reference array units are the reference bit lines when the bit lines at the upper section above the sense amplifiers formed between the top and bottom cell array units and the edge reference array units are the main bit lines. 10. The nonvolatile ferroelectric memory device of claim 9, wherein the cell array is folded symmetrically about the bit line to form an open bit line structure having the unit cells overlapped with each other. 11. The nonvolatile ferroelectric memory device of claim 9, the middle reference array unit further comprising; a plurality of bit lines disposed in a direction in a unit cell block; a reference word line disposed in a direction perpendicular to the bit lines; a reference plate line disposed in the same direction as the reference word line; a plurality of reference capacitors disposed in parallel with each other, each reference capacitor having first and second electrodes connected to the reference plate line and a reference line as a storage node, respectively; a level initialization unit including an NMOS transistor having a gate and two electrodes wherein a reference cell equalizer control signal is applied to the gate, and the two electrodes are respectively connected to a ground terminal and the reference line as the storage node; and a switching block including a plurality of transistors, wherein the transistors have gates jointly connected to the reference word line, and each transistor has one electrode connected to the respective corresponding bit lines and another electrode connected to the reference line as the storage node. 12. The nonvolatile ferroelectric memory device of claim 9, the edge reference line further comprising: a plurality of reference bit lines corresponding respectively to bit lines from the middle reference array unit; an outermost NMOS transistor and a plurality of inner NMOS transistors disposed between the reference bit lines, wherein the gate of each NMOS transistor is connected to ground level, the drain of each NMOS transistor is connected to a following reference bit line, the source of each inner NMOS transistor is connected to a preceding reference bit line; and a dummy load section, wherein a source terminal of the outermost NMOS transistor is connected to ground level. 13. A nonvolatile ferroelectric memory device comprising: top and bottom cell array units disposed at an upper and a lower sections symmetrical about a plurality of sense amplifiers, each cell array unit including a plurality of unit cells; a plurality of reference array units disposed at edge sections of the top and bottom cell array units corresponding to the sense amplifiers, respectively; a plurality of bit lines wherein two of the bit lines of the top cell array unit and two of the corresponding bit lines of the bottom cell array unit share one of the sense amplifiers, wherein the bit lines at the lower area symmetrical about the sense amplifiers are used as reference bit lines when the bit lines at the upper area symmetrical about the sense amplifiers are used as main bit lines, and wherein two bit lines adjacent to the main and reference bit lines at the upper and lower sections are used as dummy reference bit lines; and a plurality of switching devices receiving first and second control signals to control whether to connect the sense amplifiers and bit lines to each other, wherein corresponding bit lines from the upper and lower sections are symmetrical about the sense amplifiers and are controlled by the same control signal. 14. The nonvolatile ferroelectric memory device of claim 13, wherein the top and bottom cell arra y units are folded symmetrically about the bit line to form a cell array with a folded bit line structure, wherein the unit cells are disposed alternately in a non-overlapping manner with respect to each other. 15. The nonvolatile ferroelectric memory device of claim 14, wherein the cell array with the folded bit line structure further comprises: a plurality of pairs of lines consisting of a word line and a plate line disposed in parallel with each other; and a plurality of bit lines disposed in a direction perpendicular to the pairs of word and plate lines, wherein cells connected to the bit lines and word lines are disposed alternately in a non-overlapping manner with each other when the cell array is folded symmetrically about the bit line. 16. The nonvolatile ferroelectric memory device of claim 14, the cell array of the folded bit line structure, further comprising: a plurality of main bit lines disposed along a column direction of the cell array unit; a plurality of sub-bit lines disposed in the same direction as the main bit lines, each sub-bit line connected to one terminal of the unit cells; first sub-bit line switch signal (SBSW1) applying lines, second left/right sub-bit line switch signals (SBSW2_L, SBSW2_R) applying lines, sub-bit line pull-up signal (SBPU) applying lines, and sub-bit line pull-down signal (SBPD) applying lines, wherein the applying lines control whether to interconnect the sub-bit lines and the main bit lines, wherein the applying lines control whether to pull up two of the sub-bit lines by a self-boost operation, respectively, and wherein the applying lines are disposed perpendicularly to the sub-bit lines to selectively pull down the sub-bit lines, respectively; a first switching device receiving a control from the SBSW1 applying line corresponding to the column direction to activate; a second switching device receiving controls from the SBSW2_L and SBSW2_R applying lines corresponding to the column direction to transfer selectively a signal of the SBPU applying line to each of the sub-bit lines; and a third switching device receiving a control from the SBPD applying line corresponding to the column direction to pull down the sub-bit line selectively. 17. The nonvolatile ferroelectric memory device of claim 13, wherein the sense amplifiers are of a latch type, output nodes of each of the sense amplifiers are shared by every two of the bit lines from the top and bottom cell array units, and each of the sense amplifiers further comprising: a first switching transistor disposed between the output nodes and activated by an equalizer signal (EQ); second and third switching transistors disposed between the output nodes of the sense amplifier and data buses (DB/DB) and activated by a column selector signal (Yi), respectively; and fourth and fifth switching transistors disposed between the output nodes and a ground voltage terminal, and respectively controlled by the equalizer signal. 18. The nonvolatile ferroelectric memory device of claim 13, wherein the reference array unit is disposed between first and second top cell array units or between first and second bottom cell array units, and, in order to adjust an internal reference level, the reference array unit further comprising: a plurality of reference capacitors F16-1, F16-2, F16-3, F16-4, . . . , F16-n disposed in parallel with each other, the reference capacitors having first electrodes jointly connected to a reference plate line REF_PL, and second electrodes jointly connected to a reference line as a storage node; a plurality of NMOS switching transistors NI-1, NI-2, NI-3, NI-4, . . . connected between the reference ferroelectric capacitors and the bit lines of the first top or bottom cell array unit, respectively in one-to-one correspondence with a plurality of the ferroelectric capacitors, wherein odd numbered NMOS transistors NI-1, NI-3, NI-5, . . . and even numbered NMOS transistors NI-2, NI-4, NI-6, . . . are co
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