IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0663953
(2000-09-19)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
Blakely, Sokoloff, Taylor & Zafman LLP
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인용정보 |
피인용 횟수 :
3 인용 특허 :
8 |
초록
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While a controller is reading a frame, a driver prepares one or more subsequent frames. A single inform write is sent by the driver to a command register of the controller to inform the controller of completion of preparation of the subsequent frame(s). By preparing the subsequent frame(s) during th
While a controller is reading a frame, a driver prepares one or more subsequent frames. A single inform write is sent by the driver to a command register of the controller to inform the controller of completion of preparation of the subsequent frame(s). By preparing the subsequent frame(s) during the reading of the frame and by collectively batching the inform writes of the prepared subsequent frames as the single inform write, instead of sending separate individual inform writes, the reading of frame(s) by the controller is uninterrupted and a number of times that the controller has to arbitrate for bus control is minimized. This advantageously reduces bus contention and latency.
대표청구항
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While a controller is reading a frame, a driver prepares one or more subsequent frames. A single inform write is sent by the driver to a command register of the controller to inform the controller of completion of preparation of the subsequent frame(s). By preparing the subsequent frame(s) during th
While a controller is reading a frame, a driver prepares one or more subsequent frames. A single inform write is sent by the driver to a command register of the controller to inform the controller of completion of preparation of the subsequent frame(s). By preparing the subsequent frame(s) during the reading of the frame and by collectively batching the inform writes of the prepared subsequent frames as the single inform write, instead of sending separate individual inform writes, the reading of frame(s) by the controller is uninterrupted and a number of times that the controller has to arbitrate for bus control is minimized. This advantageously reduces bus contention and latency. can be used to address said first buffer is the address of a data port in the ATA transfer protocol. 13. The apparatus of claim 1, wherein said host interface also includes a second buffer operable to store data to be transmitted to said host computer and addressed by the one of said ATA command block register addresses that can be used to address said first buffer. 14. The apparatus of claim 13, wherein said second buffer is a queue or FIFO. 15. The apparatus of claim 1, wherein said first buffer is a queue or FIFO. 16. The apparatus of claim 1, wherein said optical drive controller further comprises: a path operable to allow a microcontroller, which controls reading of information from optical media, to read said first buffer. 17. The apparatus of claim 1, wherein said host interface includes a status register addressed by another of said ATA command block register addresses, said status register including a BSY bit. 18. The apparatus of claim 17, wherein said host interface alters said BSY bit when necessary to indicate when said host computer is precluded from accessing said ATA command block register addresses. 19. The apparatus of claim 17, wherein said host interface includes circuitry operable to clear the signal on an HIRQ line of said IDE/ATA bus responsive to said host computer reading said status register. 20. The apparatus of claim 17, wherein said host interface includes circuitry operable to alter said BSY bit, responsive to command events initiated by the host computer, to a state that precludes said host computer from accessing said ATA command block register addresses. 21. The apparatus of claim 20, wherein said optical drive controller further comprises: a path operable to allow a microcontroller, which controls reading of information from optical media, to alter said BSY bit to a state that allows said host computer to access said ATA command block register addresses. 22. The apparatus of claim 17, wherein said host interface is operable to assert signals on DASP and PDIAG lines of said IDE/ATA bus according to the ATA transfer protocol. 23. The apparatus of claim 22, wherein said host interface is also operable to assert signals on an HIRQ line of said IDE/ATA bus according to the ATA transfer protocol. 24. The apparatus of claim 23, wherein said host interface includes circuitry operable to carry out initial signal transitions on said DASP, PDIAG, and HIRQ lines in response to soft reset and execute drive diagnostic command events. 25. The apparatus of claim 24, wherein said optical drive controller further comprises: a path operable to allow a microcontroller, which controls reading of information from optical media, to control certain transitions of signals on said DASP, PDIAG, and HIRQ lines of said IDE/ATA bus. 26. The apparatus of claim 17, wherein said host interface is also operable to assert signals on DASP and PDIAG lines of said IDE/ATA bus responsive to power on reset or execute diagnostic commands received from said host computer. 27. The apparatus of claim 26, wherein said optical drive controller further comprises: a path operable to allow a microcontroller, which controls reading of information from optical media, to cause the assertion of signals on DASP and PDIAG lines of said IDE/ATA bus. 28. The apparatus of claim 1, wherein said host interface includes a drive/head register addressed by another of said ATA command block register addresses, said drive/head register including a DRV bit. 29. The apparatus of claim 28, wherein said host interface uses said DRV bit to determine whether to store commands in said first buffer. 30. The apparatus of claim 1, wherein said host interface is also operable to communicate control signals on at least certain control lines of said IDE/ATA bus. 31. The apparatus of claim 30, wherein said control lines include HIRQ, DASP, and PDIAG. 32. The apparatus of claim 1, wherein said host interface is also operable to assert signals on an HI RQ line of said IDE/ATA bus according to the ATA transfer protocol. 33. The apparatus of claim 1, wherein said host interface is also operable to assert signals on an HIRQ line of said IDE/ATA bus to alert said host computer during data transfers. 34. The apparatus of claim 1, wherein said host interface is also operable to assert signals on an HIRQ line of said IDE/ATA bus to allow said host computer to engage in multi-tasking. 35. An apparatus comprising: a host interface in an optical drive controller, said host interface operable to be directly connected to a host computer via an IDE/ATA bus, wherein said IDE/ATA bus has a width, said host interface including, a multi-byte command buffer addressed by one of a plurality of ATA command block register addresses and operable, per command, to store sequentially contiguous multiple command bytes received from said host computer in a single command transfer, wherein said multi-byte command buffer provides a greater amount of storage than said width; and a path in said optical drive controller operable to allow a microcontroller, which controls reading of information from optical media, to read said multi-byte command buffer. 36. The apparatus of claim 35, wherein said microcontroller is also operable to cause the assertion of signals on DASP and PDIAG lines of said IDE/ATA bus. 37. The apparatus of claim 35, wherein said microcontroller is also operable to cause the assertion of signals on an HIRQ line of said IDE/ATA bus to generate interrupts on said host computer. 38. The apparatus of claim 35, wherein said ATA command block register addresses address eight register locations. 39. The apparatus of claim 35, wherein said IDE/ATA bus includes, host address lines; and a host chip select line whose signal identifies whether signals on the host address lines are carrying one of said ATA command block register addresses. 40. The apparatus of claim 35, wherein host interface includes physical registers that are addressed by at least certain of said ATA command block register addresses. 41. The apparatus of claim 35, wherein said host interface supports all of the signals required by the ATA transfer protocol. 42. The apparatus of claim 35, wherein said IDE/ATA bus is at least 16 bits wide. 43. The apparatus of claim 35, wherein the one of said ATA command block register addresses that can be used to address said multi-byte command buffer is the address of a data port in the ATA transfer protocol. 44. The apparatus of claim 35, wherein said host interface also includes a multi-byte data buffer operable to store data to be transmitted to said host computer and addressed by the one of said ATA command block register addresses that can be used to address said multi-byte command buffer. 45. The apparatus of claim 44, wherein said multi-byte data buffer is a queue or FIFO. 46. The apparatus of claim 35, wherein said multi-byte command buffer is a queue or FIFO. 47. The apparatus of claim 35, wherein said host interface includes a status register addressed by another of said ATA command block register addresses, said status register including a BSY bit. 48. The apparatus of claim 47, wherein said host interface alters said BSY bit when necessary to indicate when said host computer is precluded from accessing said ATA command block register addresses. 49. The apparatus of claim 47, wherein said host interface includes circuitry operable to clear the signal on an HIRQ line of said IDE/ATA bus responsive to said host computer reading said status register. 50. The apparatus of claim 47, wherein said host interface includes circuitry operable to alter said BSY bit, responsive to command events initiated by the host computer, to a state that precludes said host computer from accessing said ATA command block register addresses. 51. The apparatus of claim 50, wherein said microcontroller is also operable to alter said BSY bit to a state that allows said host computer to access said AT
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