초록 ▼

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system,

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

대표청구항 ▼

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system,

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed. ion as a CFR_Flag in the CSR, where said CFR_Flag indicates whether said at least one of said previous nodes has not been reassigned one of said CHs and one of said BWs; (c1) assigning one of said CHs and one of said BWs to said at least one of the previous nodes, and recording a Node ID and the assigned BW in positions of a resource releasable register (RRR) corresponding to the assigned one of said CHs of said at least one of the previous nodes prior to starting an isochronous data communication, if said at least one of said previous nodes has not been reassigned one of said CHs and one of said BWs before said given period of time; (d1) assigning one of said CHs and one of said BWs to said new node and starting said isochronous data communication, if each of said at least one of the previous nodes has been reassigned one of said CHs and one of said BWs after said given period of time; (e1) reassigning one of said CHs and one of said BWs to said requesting node after said given period of time by releasing said one of said CHs and said one of said BWs assigned to said new node based upon the RRR, and starting said isochronous data communication, if said requesting node is said at least one of the previous nodes and if either one or both said one of said CHs and said one of said BWs are not available; and (f1) reassigning one of said CHs and one of said BWs to said requesting node after said given period of time and starting said isochronous data communication if said requesting node is said at least one of the previous nodes and if said one of said CHs and said one of said BWs are both available. 2. The method of claim 1, wherein step (a1) further comprises: copying and storing data from the CAR of the IRM into the PCAR of the IRM, and determining whether said node requesting said one of said CHs and said one of said BWs is one of either said new node or one of said at least one of the previous nodes. 3. The method of claim 2, wherein if a bit value of "0" in the CAR indicates that said one of said CHs is being used and if a bit value of "1" indicates that said one of said CHs is free, a value of "0" for the PCAR_Flag indicates said at least one of the previous nodes is present. 4. The method of claim 1, wherein step (c1) further comprises: subtracting the assigned one of said BWs from a bandwidth available register (BAR), converting a bit value of the CAR corresponding to the assigned one of said CHs, and setting a bit value of a releasable channel flag register (RCFR) corresponding to the assigned one of said CHs to a predetermined value, prior to starting said isochronous data communication, if the assigned one of said CHs had not been previously assigned prior to the bus reset; and subtracting the assigned one of said CHs from the BAR, converting a bit value of the CAR corresponding to the assigned one of said CHs prior to starting said isochronous data communication, if the assigned one of the CHs had been previously assigned prior to the bus reset. 5. The method of claim 4, wherein in step (e1), reassigning said one of said CHs and one of said BWs to said requesting node comprises: requesting a reassignment of another of said CHs and another of said BWs; requesting a release of the another of said CHs from the node recorded in a position of the RRR corresponding to the another of said CHs, if the another of said CHs is not available; adding another of said BWs recorded in the position corresponding to the another of said CHs with a free one of said BWs within the BAR of the IRM, where a sum of the BWs becomes an updated free BW within the BAR of the IRM; and requesting for a release of CH still another of said CHs and still another of said BWs from a node recorded in a position of the RRR corresponding to one of the CHs with a RCFR bit value set to the predetermined value if the sum of said BWs is not enough for reassignment to said requesting node, and otherwise re-assigning the another of sai