IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0642505
(2000-08-18)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
Blakely, Sokoloff, Taylor & Zafman LLP
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인용정보 |
피인용 횟수 :
33 인용 특허 :
73 |
초록
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A integrated circuit includes a processor, a bus coupled to the processor, a memory interface and an interface bus. The memory interface provides an interface between the bus and at least two memory devices including a first memory device and a second memory device. The interface bus is coupled to t
A integrated circuit includes a processor, a bus coupled to the processor, a memory interface and an interface bus. The memory interface provides an interface between the bus and at least two memory devices including a first memory device and a second memory device. The interface bus is coupled to the first memory device, the second memory device and the memory interface. Control signals, address signals and data signals are transmitted over the interface bus.
대표청구항
▼
A integrated circuit includes a processor, a bus coupled to the processor, a memory interface and an interface bus. The memory interface provides an interface between the bus and at least two memory devices including a first memory device and a second memory device. The interface bus is coupled to t
A integrated circuit includes a processor, a bus coupled to the processor, a memory interface and an interface bus. The memory interface provides an interface between the bus and at least two memory devices including a first memory device and a second memory device. The interface bus is coupled to the first memory device, the second memory device and the memory interface. Control signals, address signals and data signals are transmitted over the interface bus. he single inform write, instead of sending separate individual inform writes, the reading of frame(s) by the controller is uninterrupted and a number of times that the controller has to arbitrate for bus control is minimized. This advantageously reduces bus contention and latency. said second buffer is a queue or FIFO. 15. The apparatus of claim 1, wherein said first buffer is a queue or FIFO. 16. The apparatus of claim 1, wherein said optical drive controller further comprises: a path operable to allow a microcontroller, which controls reading of information from optical media, to read said first buffer. 17. The apparatus of claim 1, wherein said host interface includes a status register addressed by another of said ATA command block register addresses, said status register including a BSY bit. 18. The apparatus of claim 17, wherein said host interface alters said BSY bit when necessary to indicate when said host computer is precluded from accessing said ATA command block register addresses. 19. The apparatus of claim 17, wherein said host interface includes circuitry operable to clear the signal on an HIRQ line of said IDE/ATA bus responsive to said host computer reading said status register. 20. The apparatus of claim 17, wherein said host interface includes circuitry operable to alter said BSY bit, responsive to command events initiated by the host computer, to a state that precludes said host computer from accessing said ATA command block register addresses. 21. The apparatus of claim 20, wherein said optical drive controller further comprises: a path operable to allow a microcontroller, which controls reading of information from optical media, to alter said BSY bit to a state that allows said host computer to access said ATA command block register addresses. 22. The apparatus of claim 17, wherein said host interface is operable to assert signals on DASP and PDIAG lines of said IDE/ATA bus according to the ATA transfer protocol. 23. The apparatus of claim 22, wherein said host interface is also operable to assert signals on an HIRQ line of said IDE/ATA bus according to the ATA transfer protocol. 24. The apparatus of claim 23, wherein said host interface includes circuitry operable to carry out initial signal transitions on said DASP, PDIAG, and HIRQ lines in response to soft reset and execute drive diagnostic command events. 25. The apparatus of claim 24, wherein said optical drive controller further comprises: a path operable to allow a microcontroller, which controls reading of information from optical media, to control certain transitions of signals on said DASP, PDIAG, and HIRQ lines of said IDE/ATA bus. 26. The apparatus of claim 17, wherein said host interface is also operable to assert signals on DASP and PDIAG lines of said IDE/ATA bus responsive to power on reset or execute diagnostic commands received from said host computer. 27. The apparatus of claim 26, wherein said optical drive controller further comprises: a path operable to allow a microcontroller, which controls reading of information from optical media, to cause the assertion of signals on DASP and PDIAG lines of said IDE/ATA bus. 28. The apparatus of claim 1, wherein said host interface includes a drive/head register addressed by another of said ATA command block register addresses, said drive/head register including a DRV bit. 29. The apparatus of claim 28, wherein said host interface uses said DRV bit to determine whether to store commands in said first buffer. 30. The apparatus of claim 1, wherein said host interface is also operable to communicate control signals on at least certain control lines of said IDE/ATA bus. 31. The apparatus of claim 30, wherein said control lines include HIRQ, DASP, and PDIAG. 32. The apparatus of claim 1, wherein said host interface is also operable to assert signals on an HIRQ line of said IDE/ATA bus according to the ATA transfer protocol. 33. The apparatus of claim 1, wherein said host interface is also operable to assert signals on an HIRQ line of said IDE/ATA bus to alert said host computer during data transfers. 34. The apparatus of claim 1, wherein said host interface is also operable to assert signals on an HIRQ line of said IDE/ATA bus to allow said host computer to
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