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System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/24
출원번호 US-0501642 (2000-02-11)
우선권정보 EP-0200431 (1999-02-15)
발명자 / 주소
  • De Oliveira Kastrup Pereira, Bernardo
  • Bink, Adrianus J.
  • Hoogerbrugge, Jan
출원인 / 주소
  • Konklijke Philips Electronics N.V.
대리인 / 주소
    Ure, Mike J.
인용정보 피인용 횟수 : 79  인용 특허 : 8

초록

A processor contains a configurable functional unit that is capable of executing reconfigurable instructions, whose effect can be redefined at run-time by loading a configuration program. Reconfigurable instructions are selected in combinations of more than one different reconfigurable instruction.

대표청구항

A processor contains a configurable functional unit that is capable of executing reconfigurable instructions, whose effect can be redefined at run-time by loading a configuration program. Reconfigurable instructions are selected in combinations of more than one different reconfigurable instruction.

이 특허에 인용된 특허 (8)

  1. Lee Ruby B. (Cupertino CA) Mahon Michael J. (San Jose CA), Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward s.
  2. Lynch Thomas W., Computer system configured to translate a computer program into a second computer program prior to executing the compute.
  3. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
  4. Trimberger Stephen M., Field programmable gate array having programming instructions in the configuration bitstream.
  5. Auerbach Richard A. (Somers NY) Blades Jerry A. (Rochester MN) Byrn Jonathan W. (Rochester MN) Delp Gary S. (Rochester MN), Method and apparatus for batching the receipt of data packets.
  6. Mohan Sundararajarao ; Trimberger Stephen M., Method for configuring FPGA memory planes for virtual hardware computation.
  7. Burger Douglas C. ; Kaxiras Stefanos ; Goodman James R., Multiple processor, distributed memory computer with out-of-order processing.
  8. Trimberger Stephen M., Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page tab.

이 특허를 인용한 특허 (79)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  11. Knowles, Simon, Apparatus and method for asymmetric dual path processing.
  12. Knowles, Simon, Apparatus and method for control processing in dual path processor.
  13. Knowles, Simon, Apparatus and method for separate asymmetric control processing and data path processing in a configurable dual path processor that supports instructions having different bit widths.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  18. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  19. Schloegel, Kirk; Bhatt, Devesh, Auto-generation of concurrent code for multi-core applications.
  20. Chai, Sek M.; Bellas, Nikos; Dwyer, Malcolm R.; Lau, Erica M.; Li, Zhiyuan; Linzmeier, Daniel A., Automatic generation of streaming data interface circuit.
  21. Ramchandran,Amit, Cache for instruction set architecture using indexes to achieve compression.
  22. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  23. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  24. Gonzalez, Ricardo E.; Rudell, Richard L.; Ghosh, Abhijit; Wang, Albert R., Configuring a multi-processor system.
  25. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  26. Williams,Kenneth M; Wang,Albert, Defining instruction extensions in a standard programming language.
  27. Conner, Bryan, Dynamic priority conflict resolution in a multi-processor computer system having shared resources.
  28. Johnson, Scott D., Extension adapter.
  29. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  30. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  31. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  32. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  33. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  34. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  35. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  36. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  37. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  38. Ramchandran,Amit, Input pipeline registers for a node in an adaptive computing engine.
  39. Williams,Kenneth Mark; Johnson,Scott Daniel; McNamara,Bruce Saylors; Wang,Albert RenRui, Instruction set for efficient bit stream and byte stream I/O.
  40. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
  41. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
  42. Gonzalez,Ricardo E.; Johnson,Scott; Taylor,Derek, Long instruction word processing with instruction extensions.
  43. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  44. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  45. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  46. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  47. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  48. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  49. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  50. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  51. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  52. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  53. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  54. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  55. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  56. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  57. Metlapalli, Kumar C., Methods and systems for computing platform.
  58. Huppenthal, Jon M.; Caliga, David E., Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions.
  59. Huppenthal, Jon M.; Leskar, Paul A., Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem.
  60. Huppenthal,Jon M.; Leskar,Paul A., Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem.
  61. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  62. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  63. Arnold, Jeffrey Mark; Banta, Gareld Howard; Johnson, Scott Daniel; Wang, Albert R., Programmable logic configuration for instruction extensions.
  64. Arnold, Jeffrey Mark; Banta, Gareld Howard; Johnson, Scott Daniel; Wang, Albert R., Reconfigurable instruction set computing.
  65. Bangert,Joachim, Reprogrammable microprogram based reconfigurable multi-cell logic concurrently processing configuration and data signals.
  66. Yoda, Katsuhiro; Sugiyama, Iwao, Semiconductor integrated circuit with selected signal line coupling.
  67. Master,Paul L.; Watson,John, Storage and delivery of device features.
  68. Huppenthal, Jon M.; Seeman, Thomas R.; Burton, Lee A., Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers.
  69. Huppenthal,Jon M.; Seeman,Thomas R.; Burton,Lee A., Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format.
  70. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  71. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  72. Doering, Andreas C.; Dragone, Silvio; Herkersdorf, Andreas; Hofmann, Richard G.; Kuhlmann, Charles E., System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration.
  73. Rupp, Charle' R., System, apparatus and method for data path routing configurable to perform dynamic bit permutations.
  74. Rupp, Charle' R.; Arnold, Jeffrey M., System, apparatus and method for implementing multifunctional memory in reconfigurable data path processing.
  75. Gonzalez, Ricardo E.; Wang, Albert R., Systems and methods for selecting input/output configuration in an integrated circuit.
  76. Gonzalez, Ricardo E.; Wang, Albert R.; Banta, Gareld Howard, Systems and methods for software extensible multi-processing.
  77. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  78. Doering, Andreas C.; Dragone, Silvio; Herkersdorf, Andreas; Hofmann, Richard G.; Kuhlmann, Charles E., Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration.
  79. Arnold,Jeffrey Mark; Banta,Gareld Howard; Johnson,Scott Daniel; Wang,Albert R., Video processing system with reconfigurable instructions.
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