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Method of forming interconnects with improved barrier layer adhesion 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0097004 (2002-03-14)
발명자 / 주소
  • Ngo, Minh Van
  • Hopper, Dawn
출원인 / 주소
  • Advanced Micro Devices, Inc.
인용정보 피인용 횟수 : 4  인용 특허 : 23

초록

Semiconductor devices comprising interconnects with improved adhesion of barrier layers to dielectric layers are formed by laser thermal annealing, in N2and H2, exposed surfaces of a dielectric layer defining an opening, and then depositing Ta to form a composite layer lining the opening. Embodiment

대표청구항

1. A method of manufacturing a semiconductor device, the method comprising: forming an opening in a dielectric layer;laser thermal anneal exposed surfaces of the dielectric layer in nitrogen (N2) and hydrogen (H2) to form the N2-enriched surface region; andforming a composite barrier layer comprisin

이 특허에 인용된 특허 (23)

  1. Buchwalter Leena P. ; Callegari Alessandro Cesare ; Cohen Stephan Alan ; Graham Teresita Ordonez ; Hummel John P. ; Jahnes Christopher V. ; Purushothaman Sampath ; Saenger Katherine Lynn ; Shaw Jane , Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same.
  2. Sato Yasuhiko,JPX ; Onishi Yasunobu,JPX, Composition for underlying film and method of forming a pattern using the film.
  3. Talwar Somit ; Kramer Karl-Josef ; Verma Guarav ; Weiner Kurt, Fabrication method for reduced-dimension FET devices.
  4. Q. Z. Liu ; Bin Zhao, Fabrication of improved low-k dielectric structures.
  5. Talwar Somit ; Weiner Kurt, Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits.
  6. Aug Arthur Khoon Siah,SGX ; Chen Feng,SGX ; Li Qiong,SGX, IMD scheme by post-plasma treatment of FSG and TEOS oxide capping layer.
  7. Chua Chee Tee,SGX ; Lee Yuan-Ping,SGX ; Zhou Mei Sheng,SGX ; Chan Lap, Laser curing of spin-on dielectric thin films.
  8. You Lu ; Iacoponi John A., Low dielectric constant coating of conductive material in a damascene process for semiconductors.
  9. Venkatesan Suresh ; Smith Bradley P. ; Islam Mohammed Rabiul, Method for forming a dual inlaid copper interconnect structure.
  10. Timothy Joseph Dalton ; Stephen Edward Greco ; Jeffrey Curtis Hedrick ; Satyanarayana V. Nitta ; Sampath Purushothaman ; Kenneth Parker Rodbell ; Robert Rosenberg, Method for forming a porous dielectric material layer in a semiconductor device and device formed.
  11. Shue, Shau-Lin; Wang, Mei-Yun, Method for forming incompletely landed via with attenuated contact resistance.
  12. Ramakrishnan E. S., Method of forming a capacitor or an inductor on a substrate.
  13. Nogami Takeshi,JPX ; Brown Dirk D. ; Lopatin Sergey, Method of improving Cu damascene interconnect reliability by laser anneal before barrier polish.
  14. Murali Narasimhan ; Vikram Pavate ; Kenny King-Tai Ngan ; Xiangbing Li, Method of improving adhesion of diffusion layers on fluorinated silicon dioxide.
  15. Talwar Somit ; Verma Gaurav, Methods for annealing an integrated device using a radiant energy absorber layer.
  16. Tian Jason L. ; Karim M. Ziaul ; van Schravendijk Bart J., Methods to improve chemical vapor deposited fluorosilicate glass (FSG) film adhesion to metal barrier or etch stop/diffusion barrier layers.
  17. Hsu Wei-Yung ; Hong Qi-Zhong, Multi-stage semiconductor cavity filling process.
  18. Hichem M'Saad ; Derek R. Witty ; Manoj Vellaikal ; Lin Zhang ; Yaxin Wang, Nitrogen treatment of polished halogen-doped silicon glass.
  19. Ho Chaw Sing,SGX ; Lee Yuan Ping,SGX ; Lap Chan ; Lu Yong Feng,SGX ; Karunasiri R. P.G.,SGX, Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices.
  20. Somit Talwar ; John Cronin, Structure and method for an optical block in shallow trench isolation for improved laser anneal control.
  21. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.
  22. Randall Cher Liang Cha SG; Alex See SG; Yeow Kheng Lim SG; Tae Jong Lee ; Lap Chan, Versatile copper-wiring layout design with low-k dielectric integration.
  23. Chung-Shi Liu TW; Shau-Lin Shue TW; Chen-Hua Yu TW, Via RC improvement for copper damascene and beyond technology.

이 특허를 인용한 특허 (4)

  1. Marathe, Amit; Wang, Connie Pin-Chin; Woo, Christy Mei-Chu; King, Paul L., Composite barrier layers with controlled copper interface surface roughness.
  2. Tonegawa, Takashi; Arita, Koji; Usami, Tatsuya; Morita, Noboru; Ohto, Koichi; Sasaki, Yoichi; Ohnishi, Sadayuki; Kitao, Ryohei, Manufacturing method of semiconductor device.
  3. Liu, Ai-Sen; Jang, Syun-Ming, Method for forming dielectric barrier layer in damascene structure.
  4. Choi, Kyeong-Keun, Method for forming metal interconnection in image sensor.
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