IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0392482
(2003-03-19)
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발명자
/ 주소 |
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출원인 / 주소 |
- The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
4 인용 특허 :
2 |
초록
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A spacecraft docks with a spinning and/or rotating asteroid, meteoroid, comet, or other space object, utilizing a tether shaped in a loop and utilizing subvehicles appropriately to control loop instabilities. The loop is positioned about a portion of the asteroid and retracted thereby docking the sp
A spacecraft docks with a spinning and/or rotating asteroid, meteoroid, comet, or other space object, utilizing a tether shaped in a loop and utilizing subvehicles appropriately to control loop instabilities. The loop is positioned about a portion of the asteroid and retracted thereby docking the spacecraft to the asteroid, meteoroid, comet, or other space object. A deployable rigidized, photon momentum transfer plane of sufficient thickness may then be inflated and filled with foam. This plane has a reflective surface that assists in generating a larger momentum from impinging photons. This plane may also be moved relative to the spacecraft to alter the forces acting on it, and thus on the asteroid, meteoroid, comet, or other space object to which it is attached. In general, these forces may be utilized, over time, to alter the orbits of asteroids, meteoroids, comets, or other space objects. Sensors and communication equipment may be utilized to allow remote operation of the rigidized, photon momentum transfer plane and tether.
대표청구항
▼
A spacecraft docks with a spinning and/or rotating asteroid, meteoroid, comet, or other space object, utilizing a tether shaped in a loop and utilizing subvehicles appropriately to control loop instabilities. The loop is positioned about a portion of the asteroid and retracted thereby docking the sp
A spacecraft docks with a spinning and/or rotating asteroid, meteoroid, comet, or other space object, utilizing a tether shaped in a loop and utilizing subvehicles appropriately to control loop instabilities. The loop is positioned about a portion of the asteroid and retracted thereby docking the spacecraft to the asteroid, meteoroid, comet, or other space object. A deployable rigidized, photon momentum transfer plane of sufficient thickness may then be inflated and filled with foam. This plane has a reflective surface that assists in generating a larger momentum from impinging photons. This plane may also be moved relative to the spacecraft to alter the forces acting on it, and thus on the asteroid, meteoroid, comet, or other space object to which it is attached. In general, these forces may be utilized, over time, to alter the orbits of asteroids, meteoroids, comets, or other space objects. Sensors and communication equipment may be utilized to allow remote operation of the rigidized, photon momentum transfer plane and tether. r circuit into commands suitable for transmission on a peripheral bus and to translate said commands suitable for transmission on a peripheral bus into packet commands; anda second buffer circuit coupled to receive said packet commands from said bus interface circuit, wherein said second buffer circuit includes a second plurality of buffers each corresponding to a respective virtual channel of said plurality of virtual channels for storing selected packet commands that belong to said respective virtual channel.2. The peripheral interface circuit as recited in claim 1 further comprising a control logic unit coupled to said first buffer circuit and said second buffer circuit and configured to control the conveyance of said packet commands to and from said bus interface circuit.3. The peripheral interface circuit as recited in claim 2 further comprising a tag logic unit coupled to said first buffer circuit and configured to receive said packet commands and to generate a tag value for each of said packet commands, wherein said tag value corresponds to the order of receipt of each of said packet commands relative to other packet commands.4. The peripheral interface circuit as recited in claim 3, wherein said tag logic unit is further configured to append said tag value to each of said packet commands prior to storage of each of said packet commands in said first buffer circuit.5. The peripheral interface circuit as recited in claim 4 further comprising an arbitration logic unit coupled to said first buffer circuit and configured to arbitrate between said packet commands stored in said first plurality of buffers depending upon said tag value for each of said control commands.6. The peripheral interface circuit as recited in claim 5 further comprising a first data buffer circuit coupled to receive packet data from said first source, wherein said first data buffer circuit is configured to receive data at a clock speed of said input/output node, and wherein data is retrieved from said first data buffer circuit at a clock speed of said peripheral bus.7. The peripheral interface circuit as recited in claim 6 further comprising a second data buffer circuit coupled to receive packet data from said bus interface circuit, wherein said second data buffer circuit is configured to receive data at a clock speed of said peripheral bus, and wherein data is retrieved from said second data buffer circuit at a clock speed of said input/output node.8. The peripheral interface circuit as recited in claim 7 further comprising a control command generator unit coupled to said second buffer circuit and configured to generate a control command for each of said packet commands received from said bus interface circuit, wherein each said control commands contains a subset of each corresponding packet command.9. The peripheral interface circuit as recited in claim 8, wherein said plurality of virtual channels includes a posted channel, a non-posted channel and a response channel which correspond to posted, a non-posted and a response packet commands, respectively.10. The peripheral interface circuit as recited in claim 9, wherein said peripheral bus is a peripheral component interconnect (PCI) bus.11. The peripheral interface circuit as recited in claim 10 further comprising a non-posted retry queue coupled to said first buffer circuit and configured to store a non-posted packet command which has been selected by said arbitration logic unit and for which a retry indication has been asserted by a peripheral device connected to said PCI bus in response to a non-posted cycle having been initiated on said PCI bus.12. The peripheral interface circuit as recited in claim 8, wherein said peripheral bus is a PCI-X bus.13. The peripheral interface circuit as recited in claim 12 further comprising a split response queue coupled to said non-posted retry queue and configured to store an indication of a non-posted cycle initiation on said periphe
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