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A steering wheel alignment system for a vehicle includes an outer shaft for operative connection to a steering unit and an inner shaft for operative connection to a steering wheel. The steering wheel alignment system also includes a coupling disposed between the inner shaft and outer shaft to allow

A steering wheel alignment system for a vehicle includes an outer shaft for operative connection to a steering unit and an inner shaft for operative connection to a steering wheel. The steering wheel alignment system also includes a coupling disposed between the inner shaft and outer shaft to allow engagement and disengagement between the steering wheel and the steering unit for alignment of the steering wheel with wheels of the vehicle.

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A steering wheel alignment system for a vehicle includes an outer shaft for operative connection to a steering unit and an inner shaft for operative connection to a steering wheel. The steering wheel alignment system also includes a coupling disposed between the inner shaft and outer shaft to allow

A steering wheel alignment system for a vehicle includes an outer shaft for operative connection to a steering unit and an inner shaft for operative connection to a steering wheel. The steering wheel alignment system also includes a coupling disposed between the inner shaft and outer shaft to allow engagement and disengagement between the steering wheel and the steering unit for alignment of the steering wheel with wheels of the vehicle. t incurring said delay.4. The apparatus as recited in claim 3, wherein said speculative operand calculation logic comprises:addition logic, configured sum a first source operand with a second source operand, said source operands being prescribed by the first preceding micro instruction; andan arithmetic opcode decoder, configured to direct said addition logic to sum said source operands if the first arithmetic operation prescribed by the first preceding micro instruction is an addition operation.5. The apparatus as recited in claim 4, wherein said speculative operand calculation logic further comprises:subtraction logic, coupled to said arithmetic opcode decoder, configured to subtract said second source operand from said first source operand;wherein, if the first arithmetic operation is a subtraction operation, said arithmetic opcode decoder directs said subtraction logic to subtract said second source operand from said first source operand.6. A speculative operand apparatus in a pipeline microprocessor, comprising: address stage logic, for generating a memory address prescribed by an address-dependent micro instruction, wherein said address stage logic comprises:a speculative address operand calculator, for generating interim results by performing arithmetic operations prescribed by preceding micro instructions, wherein said interim results comprise a first interim result that is generated by performing a first arithmetic operation prescribed by a first preceding micro instruction, and wherein said arithmetic operations are performed prior to generation of final results by executing said preceding micro instructions;a speculative operand cache, coupled to said address stage logic, for temporarily storing said interim results; andspeculative operand configuration logic, coupled to said speculative operand cache, for accessing one or more of said interim results to configure a speculative address operand corresponding to contents of a register prescribed by said address-dependent micro instruction, thereby permitting said memory address to be generated in lieu of a stall.7. The speculative operand apparatus as recited in claim 6, wherein said final results are generated when said preceding micro instructions are executed by execute logic within the pipeline microprocessor, and wherein said final results are stored in corresponding registers for access by following micro instructions.8. The speculative operand apparatus as recited in claim 7, wherein said speculative address operand calculator comprises:an adder, for summing a first source operand with a second source operand, said source operands being prescribed by said first preceding micro instruction; and arithmetic opcode decoding logic, configured to direct said adder to sum said source operands if said first arithmetic operation is an addition operation.9. The speculative operand apparatus as recited in claim 8, wherein said speculative address operand calculator further comprises:a subtractor, coupled to said arithmetic opcode decoding logic, for subtracting said second source operand from said first source operand;wherein, if said first arithmetic operation is a subtraction operation, said arithmetic opcode decoding logic directs said subtractor to subtract said second source operand from said first source operand.10. The speculative operand apparatus as recited in claim 9, wherein said preceding micro instructions correspond to one of the following x86 macro instructions: ADD, MOV, INC, SUB, or DEC.