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Method of forming local interconnects 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0001758 (2001-10-24)
발명자 / 주소
  • Abbott, Todd R.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Wells St. John P.S.
인용정보 피인용 횟수 : 15  인용 특허 : 25

초록 ▼

A first dielectric layer is formed over a first transistor gate and a second transistor source/drain region. Contact openings are formed in the first dielectric layer to the first transistor gate and to the second transistor source/drain region. A second dielectric layer is formed over the first die

대표청구항 ▼

A first dielectric layer is formed over a first transistor gate and a second transistor source/drain region. Contact openings are formed in the first dielectric layer to the first transistor gate and to the second transistor source/drain region. A second dielectric layer is formed over the first die

이 특허에 인용된 특허 (25)

  1. Trivedi, Jigish D.; Wang, Zhongze; Abbott, Todd R.; Cho, Chih-Chen, Cross-diffusion resistant dual-polycide semiconductor structure and method.
    상세보기
  2. Manning H. Montgomery, Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines.
    상세보기
  3. Todd R. Abbott ; Michael P. Violette ; Charles H. Dennison, METHOD OF FORMING A LOCAL INTERCONNECT, METHOD OF FABRICATING INTEGRATED CIRCUITRY COMPRISING AN SRAM CELL HAVING A LOCAL INTERCONNECT AND HAVING CIRCUITRY PERIPHERAL TO THE SRAM CELL, AND METHOD OF .
    상세보기
  4. Wong Siu-Weng S. (Ithaca NY) Chen Devereaux C. (San Jose CA) Chiu Kuang-Yi (Los Altos Hills CA), Method for making silicide interconnection structures for integrated circuit devices.
    상세보기
  5. Hsu Sheng Teng, Method for manufacturing a CMOS self-aligned strapped interconnection.
    상세보기
  6. Nagashima Naoki,JPX, Method of fabricating semiconductor device.
    상세보기
  7. Li Li ; Hu Yongjun Jeff, Method of forming a conductive line and method of forming a local interconnect.
    상세보기
  8. Abbott, Todd R.; Wang, Zhongze; Trivedi, Jigish D.; Cho, Chih-Chen, Method of forming a field effect transistor.
    상세보기
  9. Ngo Minh Van ; Besser Paul R. ; Liu Yowjuang Bill, Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide.
    상세보기
  10. Mark Fischer ; Jigish D. Trivedi ; Charles H. Dennison ; Todd R. Abbott ; Raymond A. Turi, Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications.
    상세보기
  11. Chen Min-Liang (Allentown PA), Method of making electrical contacts to gate structures in integrated circuits.
    상세보기
  12. Abbott, Todd; Trivedi, Jigish D.; Violette, Mike; Dennison, Chuck, Method of selectively forming local interconnects using design rules.
    상세보기
  13. Abbott, Todd; Trivedi, Jigish D.; Violette, Mike; Dennison, Chuck, Method of selectively forming local interconnects using design rules.
    상세보기
  14. Abbott Todd R. ; Violette Michael P. ; Dennison Charles H., Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of f.
    상세보기
  15. Verrett Douglas P. (Sugarland TX), Polycide local interconnect method and structure.
    상세보기
  16. O'Brien Sean ; Prinslow Douglas A., Self-aligned silicide process.
    상세보기
  17. Wieczorek Karsen ; Hause Frederick N., Semiconductor device having elevated silicidation layer and process for fabrication thereof.
    상세보기
  18. Kaoru Mikagi JP, Semiconductor device having silicide films on a gate electrode and a diffusion layer and manufacturing method thereof.
    상세보기
  19. Kimura Masatoshi,JPX, Semiconductor device with particular silicide structure.
    상세보기
  20. Hu Yongjun Jeff, Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line.
    상세보기
  21. En William G. ; Ngo Minh Van ; Yang Chih-Yuh ; Foote David K. ; Bell Scott A. ; Karlsson Olov B. ; Lyons Christopher F., Silicon oxime spacer for preventing over-etching during local interconnect formation.
    상세보기
  22. Gualandris Fabio,ITX ; Maggis Aldo,ITX, Surface field effect transistor with depressed source and/or drain areas for ULSI integrated devices.
    상세보기
  23. Shepela Adam ; Grula Gregory J. ; Zetterlund Bjorn, Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions.
    상세보기
  24. Li Weidan ; Yeh Wen-Chin ; Rakkhit Rajat, Tungsten local interconnect for silicon integrated circuit structures, and method of making same.
    상세보기
  25. Liaw Jhon-Jhy,TWX, Tungsten local interconnect, using a silicon nitride capped self-aligned contact process.
    상세보기

이 특허를 인용한 특허 (15)

  1. Abbott, Todd, Flash memory with recessed floating gate.
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  2. Abbott, Todd, Flash memory with recessed floating gate.
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  3. Abbott, Todd, Flash memory with recessed floating gate.
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  4. Abbott, Todd, Flash memory with recessed floating gate.
    상세보기
  5. Abbott,Todd, Flash memory with recessed floating gate.
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  6. Forbes, Leonard, Memory array and memory device.
    상세보기
  7. Forbes, Leonard, Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines.
    상세보기
  8. Forbes, Leonard, Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines.
    상세보기
  9. Forbes, Leonard, Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines.
    상세보기
  10. Forbes, Leonard, Method of making a memory array with surrounding gate access transistors and capacitors with global staggered local bit lines.
    상세보기
  11. Abbott, Todd; Tirvedi, Jigish D.; Violette, Mike; Dennison, Chuck, Method of selectively forming local interconnects using design rules.
    상세보기
  12. Forbes, Leonard, Surround gate access transistors with grown ultra-thin bodies.
    상세보기
  13. Forbes, Leonard, Surround gate access transistors with grown ultra-thin bodies.
    상세보기
  14. Forbes, Leonard, Surround gate access transistors with grown ultra-thin bodies.
    상세보기
  15. Forbes, Leonard, Surround gate access transistors with grown ultra-thin bodies.
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