IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0068801
(2002-02-05)
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발명자
/ 주소 |
- Newhouse, Thomas J.
- Martin, David B.
- Breuker, Kevin Scott
- Dinneweth, Mark James
- Van Weiren, Steven M.
- Verkaik, Thomas L.
|
출원인 / 주소 |
|
대리인 / 주소 |
Brinks Hofer Gilson & Lione
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인용정보 |
피인용 횟수 :
36 인용 특허 :
133 |
초록
▼
A stackable wall panel assembly including a lower wall panel having a top, a bottom, vertically extending ends and opposite sides and an upper wall panel having a top, a bottom, vertically extending ends and opposite sides. A vertically extending stanchion has a lower end connected to the top of the
A stackable wall panel assembly including a lower wall panel having a top, a bottom, vertically extending ends and opposite sides and an upper wall panel having a top, a bottom, vertically extending ends and opposite sides. A vertically extending stanchion has a lower end connected to the top of the lower wall panel and an upper end connected to the bottom of the upper wall panel. The bottom of the upper wall panel is spaced from the top of the lower wall panel to form an open space between the upper and lower wall panels. In a preferred embodiment, a rail extends between the stanchions. Also in a preferred embodiment, a cover covers the space formed between the upper and lower wall panels. In another aspect, a second stanchion is connected to the top of the upper wall panel and a second upper wall panel is connected to the top of the second stanchion. In one preferred embodiment, draw members connect the first upper wall panel to the first stanchion and connect the second upper wall panel to the second stanchion. Alternatively, a draw block, insert and draw rod are used to connect the first upper wall panel to the lower wall panel, and to connect the first and second upper wall panels. In another aspect, a draw rod connects a lower connector post to a first upper connector post, with a spacer post disposed therebetween. A method for assembling a stackable wall panel assembly is also provided.
대표청구항
▼
A stackable wall panel assembly including a lower wall panel having a top, a bottom, vertically extending ends and opposite sides and an upper wall panel having a top, a bottom, vertically extending ends and opposite sides. A vertically extending stanchion has a lower end connected to the top of the
A stackable wall panel assembly including a lower wall panel having a top, a bottom, vertically extending ends and opposite sides and an upper wall panel having a top, a bottom, vertically extending ends and opposite sides. A vertically extending stanchion has a lower end connected to the top of the lower wall panel and an upper end connected to the bottom of the upper wall panel. The bottom of the upper wall panel is spaced from the top of the lower wall panel to form an open space between the upper and lower wall panels. In a preferred embodiment, a rail extends between the stanchions. Also in a preferred embodiment, a cover covers the space formed between the upper and lower wall panels. In another aspect, a second stanchion is connected to the top of the upper wall panel and a second upper wall panel is connected to the top of the second stanchion. In one preferred embodiment, draw members connect the first upper wall panel to the first stanchion and connect the second upper wall panel to the second stanchion. Alternatively, a draw block, insert and draw rod are used to connect the first upper wall panel to the lower wall panel, and to connect the first and second upper wall panels. In another aspect, a draw rod connects a lower connector post to a first upper connector post, with a spacer post disposed therebetween. A method for assembling a stackable wall panel assembly is also provided. e buried layer(26) of thepower transistor and said base of theintegrated control circuit transistor, respectively ;and characterized by the fact that the formation of the regions (21), (19), (13) and (14) of the base (15) and of the emitter (16) of the transistor of the integrated control circuit is preceded by the epitaxial growth of a semiconductor layer (17) of the first type of conductivity. (g) epitaxially growing another semiconductor layer of the first type of conductivity before the performing the steps of forming the regions in steps (d), (e) and (f).2. A manufacturing process as claimed in claim 1characterized by the fact that the region (15) of the base of aforesaid integrated control circuit transistor extendsincluding the step ofextending from the surface(12) ofaforesaidsaid another semiconductorlayer(17) as far as the buried layer(26) ofthesaidcollector region of saidintegrated control circuittransistor. 3. A process for manufacturing a monolithic semiconductor device that includes a three region vertical structure and a power transistor integrated on the same chip, the steps comprising: (a) epitaxially growing on a semiconductor substrate of a first type of conductivity a semiconductor layer which is the same type of conductivity as said semiconductor substrate; (b) simultaneously forming within the surface of said semiconductor layer a first semiconductor region of a second type of conductivity and a second semiconductor region of said second type of conductivity, said first region constituting a base region of the power transistor, said second region constituting a horizontal insulating region for a portion of the integrated circuit; (c) simultaneously forming within the surface of said first and second regions two other regions of the first type of conductivity, constituting, respectively, the emitter region of the power transistor and a buried layer; (d) epitaxially growing a second semiconductor layer of said first type of conductivity, at least a portion of said second layer being above and next to said buried layer thereby becoming a bottom region of said three region vertical structure; (e) forming a third region of said second conductivity type in said second layer, at least a portion of said third region being above and next to said bottom region of the three region vertical structure, said third region thereby becoming a middle layer of said three region vertical structure; (f) forming a fourth region of said first conductivity type in said middle region, said fourth region thereby becoming a top region of the three region vertical structure; and (g) simultaneously forming connecting regions from the top surface of said second layer to said horizontal insulating region and to said base region of the power transistor respectively. 4. A manufacturing process as claimed inclaim 3 including the step of forming a connecting region from the top surface of said second layer to said buried layer. st data stream are assigned. Also, data of the second data stream are assigned to the signal points of each signal point group. A difference in the transmission error rate between first and second data streams is developed by shifting the signal points to other positions in the space diagram expressed at least in the polar coordinate system. At the receiver side, the first and/or second data streams can be reconstructed from a received signal. In TV broadcast service, a TV signal is divided by a transmitter into, low and high, frequency band components which are designated as a first and a second data streams respectively. Upon receiving the TV signal, a receiver can reproduce only the low frequency band component or both the low and high frequency band components, depending on its capability. Furthermore, a communication system based on an OFDM system is utilized for data transmission of a plurality of subchannels, wherein the subchannels are differentiated by changing the length of a guard time slot or a carrier wave interval of a symbol transmission time slot, or changing the transmission electric power of the carrier.
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