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A rolling wheel testing apparatus includes a spindle assembly adapted to support a tire and wheel assembly for rotation. The spindle assembly includes an output shaft end having a plurality of holes extending into the shaft end substantially parallel to an axis of rotation of the spindle assembly. A

A rolling wheel testing apparatus includes a spindle assembly adapted to support a tire and wheel assembly for rotation. The spindle assembly includes an output shaft end having a plurality of holes extending into the shaft end substantially parallel to an axis of rotation of the spindle assembly. A plurality of signal wires are provided in particular. A signal wire is disposed in each of the holes.

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A rolling wheel testing apparatus includes a spindle assembly adapted to support a tire and wheel assembly for rotation. The spindle assembly includes an output shaft end having a plurality of holes extending into the shaft end substantially parallel to an axis of rotation of the spindle assembly. A

A rolling wheel testing apparatus includes a spindle assembly adapted to support a tire and wheel assembly for rotation. The spindle assembly includes an output shaft end having a plurality of holes extending into the shaft end substantially parallel to an axis of rotation of the spindle assembly. A plurality of signal wires are provided in particular. A signal wire is disposed in each of the holes. in a group of N data bits comprising: an input stage of 4:3 carry-save adders, each of said 4:3 carry-save adders receiving four of said N data bits on four input lines and generating three sum bits (S 2, S1, S0) equal to a total number of Logic 1 bits on said four input lines, wherein said three sum bits have bit weights of S2=4, S1=2 and S0=1, respectively; a first intermediate stage of 4:2 carry-save adders, each of said first intermediate stage 4:2 carry-save adders having four input lines for receiving selected ones of said S 2 sum bits, said S1 sum bits, and said S0 sum bits and generating therefrom a carry-out (COUT) bit, a carry (C) bit and a sum (S) bit; and a carry-propagate adder having a first input channel and a second input channel coupled to said first intermediate stage 4:2 carry-save adders and capable of generating a binary result equal to a total number of Logic 1 bits in said group of N data bits. 2. The circuit for determining the number of Logic 1 bits as set forth in claim 1 wherein N equals 16 and said input stage comprises four 4:3 carry-save adders.3. The circuit for determining the number of Logic 1 bits as set forth in claim 2 wherein said intermediate stage comprises three 4:2 carry-save adders.4. The circuit for determining the number of Logic 1 bits as set forth in claim 1 wherein N equals 32 and said input stage comprises eight 4:3 carry-save adders.5. The circuit for determining the number of Logic 1 bits as set forth in claim 4 further comprising a second intermediate stage of 4:2 carry-save adders, each of said second intermediate stage 4:2 carry-save adders having four input lines for receiving selected ones of said COUT bits, said C-bits, and said S-bits from said first intermediate stage 4:2 carry-save adders.6. A circuit for determining the number of Logic 1 bits in a group of N data bits comprising: an input stage of 6:3 carry-save adders, each of said 6:3 carry-save adders receiving six of said N data bits on six input lines and generating three sum bits (S 2, S1, S0) equal to a total number of Logic 1 bits on said six input lines, wherein said three sum bits have bit weights of S2=4, S1=2 and S0=1, respectively; a first intermediate stage of 4:2 carry-save adders, each of said first intermediate stage 4:2 carry-save adders having four input lines for receiving selected ones of said S 2 sum bits, said S1 sum bits, and said S0 sum bits and generating therefrom a carry-out (COUT) bit, a carry (C) bit and a sum (S) bit; and a carry-propagate adder having a first input channel and a second input channel coupled to said first intermediate stage 4:2 carry-save adders and capable of generating a binary result equal to a total number of Logic 1 bits in said group of N data bits. 7. The circuit for determining the number of Logic 1 bits as set forth in claim 6 wherein N equals 16 and said input stage comprises three 6:3 carry-save adders.8. The circuit for determining the number of Logic 1 bits as set forth in claim 7 wherein said intermediate stage comprises three 4:2 carry-save adders.9. The circuit for determining the number of Logic 1 bits as set forth in claim 6 wherein N equals 32 and said input stage comprises six 6:3 carry-save adders.10. The circuit for determining the number of Logic 1 bits as set forth in claim 9 further comprising a second intermediate stage of 4:2 carry-save adders, each of said second intermediate stage 4:2 carry-save adders having four input lines for receiving selected ones of said COUT bits, said C-bits, and said S-bits from said first intermediate stage 4:2 carry-save adders.11. A circuit for determining the number of Logic 1 bits in a group of N data bits comprising: an input stage of 8:4 carry-save adders, each of said 8:4 carry-save adders receiving eight of said N data bits on eight input lines and generating four sum bits (S 3, S2, S1, S0) equal to a total number of Logic 1 bits on said eight input lines, wherein said four sum bits have bi