초록 ▼

A dynamic battery array of individual cells, controllably interconnected for instantaneous dynamic configuration into a plurality of individual power buses having different electrical power output characteristics, each of which is tailored to supply the electrical power required at the instant by a

A dynamic battery array of individual cells, controllably interconnected for instantaneous dynamic configuration into a plurality of individual power buses having different electrical power output characteristics, each of which is tailored to supply the electrical power required at the instant by a particular electrical load within a circuit. Preferably the cells are fungible and randomly available so that at any given instant any given cell can be poweringly associated with a particular electrical load. The dynamic battery array, consisting of discrete cells lends itself to mounting on physically flexible substrates such as credit cards. The programmable array employs low resistance switch arrays for dynamically and instantaneously forming individual power networks or power buses between selected power cells and individual electrical loads in electrical circuits. The circuits to which such battery arrays are applied are generally complex circuits in which several different loads occur, each of which has a different power requirement.

대표청구항 ▼

A dynamic battery array of individual cells, controllably interconnected for instantaneous dynamic configuration into a plurality of individual power buses having different electrical power output characteristics, each of which is tailored to supply the electrical power required at the instant by a

A dynamic battery array of individual cells, controllably interconnected for instantaneous dynamic configuration into a plurality of individual power buses having different electrical power output characteristics, each of which is tailored to supply the electrical power required at the instant by a particular electrical load within a circuit. Preferably the cells are fungible and randomly available so that at any given instant any given cell can be poweringly associated with a particular electrical load. The dynamic battery array, consisting of discrete cells lends itself to mounting on physically flexible substrates such as credit cards. The programmable array employs low resistance switch arrays for dynamically and instantaneously forming individual power networks or power buses between selected power cells and individual electrical loads in electrical circuits. The circuits to which such battery arrays are applied are generally complex circuits in which several different loads occur, each of which has a different power requirement. ectrode to a gate electrode through a contact-hole provided in a portion of a semiconductor layer forming said thin film transistor, and wherein a passivation film patterned to have a width equal to that of said back channel electrode and said semiconductor layer are provided between said back channel and a gate insulating film. 8. A thin film transistor including: a back channel electrode, wherein a voltage of a front channel positioned on the side of a gate wiring of said thin film transistor is made equal to a voltage of said back channel positioned on the side of a back channel electrode by short-circuiting said back channel electrode to a gate electrode through a contact-hole provided in a portion of semiconductor layer forming said thin film transistor, and wherein said semiconductor layer patterned to have a width equal to that of source and drain electrodes of said thin film transistor is provided between said source and drain electrodes and a gate insulating film. 9. A thin film transistor including a back channel electrode, wherein a voltage of a front channel positioned on the side of a gate wiring of said thin film transistor is made equal to a voltage of said back channel positioned on the side of a back channel electrode by short-circuiting said back channel electrode to a gate electrode through a contact-hole provided in a potion of a layer forming said thin film transistor, and wherein said contact-hole is formed in a location remote from an active region of said thin film transistor by at least five microns. 10. A thin film transistor including a back channel electrode, wherein a voltage of a front channel positioned on the side of a gate wiring of said thin film transistor is made equal to a voltage of said back channel positioned on the side of a back channel electrode by short-circuiting said back channel electrode to a gate electrode through a contact-hole provided in a portion of a layer forming said thin film transistor, and wherein a passivation film patterned to have a width equal to that of said back channel electrode and said layer are provided between said back channel and a gate insulating film of said film transistor. 11. A thin film transistor including: a back channel electrode, wherein a voltage of a front channel positioned on the side of a gate wiring of said thin film transistor is made equal to a voltage of said back channel positioned on the side of a back channel electrode by short-circuiting said back channel electrode to a gate electrode through a contact-hole provided in a portion of a semiconductor layer forming said thin film transistor, and wherein said layer patterned to have a width equal to that of source and drain electrodes of said thin film transistor is provided between said source and drain electrodes and a gate insulating film of said film transistor. 12. A thin film transistor including: a back channel electrode, wherein a voltage of a front channel positioned on the side of a gate wiring of said thin film transistor is made equal to a voltage of said back channel positioned on the side of a back channel electrode by short-circuiting said back channel electrode to a gate electrode through a contact-hole provided in a portion of a semiconductor layer forming said thin film transistor, and wherein said layer has an ohmic contact layer on the side thereof, which is in contact with source and drain electrodes of said film transistor. 13. A thin film transistor as claimed in claim 12, wherein said portion of said semiconductor layer forming said thin film transistor contact-hole for short-circuiting said back gate electrode ands said gate electrode comprises an active layer. vity with respect to a bit line interlayer insulating layer deposited after said bit lines are formed, and disposed on sides of an upper surface of each said enlarged width portion to protect sides of said enlarged width portions; an interlayer insulating layer and at least a portion of an etch stop layer disposed between said bit lines and transistors of a substrate; and metal contact pads formed along with bit line contact plugs to pass through said interlayer insulating layer and said etch stop layer. nductive layer contact structure according to claim 1, wherein said sidewall insulation film has a high etching selectivity with respect to said first insulation layer.3. The semiconductor device having a conductive layer contact structure according to claim 1, wherein said first insulation layer includes upper and lower insulation layers, and said second insulation layer has a high etching selectivity with respect to the upper insulation layer of said first insulation layer.4. The semiconductor device having a conductive layer contact structure according to claim 3, wherein said sidewall insulation film has a high etching selectivity with respect to the upper insulation layer of said first insulation layer.5. The semiconductor device having a conductive layer contact structure according to claim 3, wherein said first hole is defined by the inner sidewall of the lower insulation layer of said first insulation layer while said second hole is defined by the inner sidewall of the upper insulation layer of said first insulation layer and the inner sidewall of said second insulation layer, said sidewall insulation film being formed at the inner sidewall of the upper insulation layer of said first insulation layer and the inner sidewall of said second insulation layer.6. The semiconductor device having a conductive layer contact structure according to claim 5, wherein said second hole includes a third hole defined by the inner sidewall of the upper insulation layer of said first insulation layer and a fourth hole smaller than said third hole defined by the inner sidewall of said second insulation layer.7. A semiconductor device having a conductive layer contact structure, comprising: first conductive layers formed on a main surface of a semiconductor substrate with an insulating film therebetween; a conductive region formed under and between said first conductive layer extending into the semiconductor substrate from, and having a junction surface intersecting, the main surface of said semiconductor substrate; a first insulation layer formed over an upper surface of said first conductive layer, having two side surfaces, one of said side surfaces reaching a surface of said conductive region and the other of said side surfaces not reaching said surface of said conductive region; a second insulation layer, having side surfaces, formed on said first insulation layer with a high etching selectivity with respect to said first insulation layer; a first hole defined by the one of said side surfaces of said first insulation layer that reaches said surface of said conductive region; a second hole defined by the side surfaces of said second insulation layer larger than said first hole and being in communication with said first hole; and a second conductive layer formed inside said first and second holes so as to be electrically connected to said conductive region and to be electrically insulated from said first conductive layer, wherein the one of said side surfaces of the first insulation layer defining the first hole is not aligned with the junction surface of the conductive region and the semiconductor substrate. 8. The semiconductor device having a conductive layer contact structure according to claim 7, wherein said first insulation layer includes upper and lower insulation layers, and said second insulation layer has a high etching selectivity with respect to the upper insulation layer of said first insulation layer.9. The semiconductor device having a conductive layer contact structure according to claim 7, further including a sidewall insulation film formed at an inner sidewall of said second insulation layer defining said second hole.10. The semiconductor device having a conductive layer contact structure according to claim 9, wherein said sidewall insulation film has a high etching selectivity with respect to said first insulation layer.11. The semiconductor device having a conductive layer contact structure accor ding to claim 8, further including a sidewall insulation film formed at an inner sidewall of said second insulation layer defining said second hole.12. The semiconductor device having a conductive layer contact structure according to claim 11, wherein said sidewall insulation film has a high etching selectivity with respect to the upper insulation layer of said first insulation layer.13. The semiconductor device having a conductive layer contact structure according to claim 7, wherein said second hole exists at a location overlapping a portion of said first conductive layer.