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A capacitive sensor system for controlling operation of a device in response to a rate of change in capacitance due to motion of a proximate object includes at least two sense electrodes disposed on a surface and a phase locked loop, including a voltage controlled oscillator and a phase/frequency co

A capacitive sensor system for controlling operation of a device in response to a rate of change in capacitance due to motion of a proximate object includes at least two sense electrodes disposed on a surface and a phase locked loop, including a voltage controlled oscillator and a phase/frequency comparator, connected between the sense electrodes and an RC network for providing an operating frequency to the sense electrodes. A circuit loop, including a reference oscillator, provides a fixed frequency reference for the phase locked loop to follow and a phase delay circuit connected between said phase/frequency comparator and said voltage controlled oscillator causes the voltage controlled oscillation to run ahead of the reference oscillator. A trigger circuit provides a control output in response to a change in phase shift between said fixed frequency and said operating frequency.

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A capacitive sensor system for controlling operation of a device in response to a rate of change in capacitance due to motion of a proximate object includes at least two sense electrodes disposed on a surface and a phase locked loop, including a voltage controlled oscillator and a phase/frequency co

A capacitive sensor system for controlling operation of a device in response to a rate of change in capacitance due to motion of a proximate object includes at least two sense electrodes disposed on a surface and a phase locked loop, including a voltage controlled oscillator and a phase/frequency comparator, connected between the sense electrodes and an RC network for providing an operating frequency to the sense electrodes. A circuit loop, including a reference oscillator, provides a fixed frequency reference for the phase locked loop to follow and a phase delay circuit connected between said phase/frequency comparator and said voltage controlled oscillator causes the voltage controlled oscillation to run ahead of the reference oscillator. A trigger circuit provides a control output in response to a change in phase shift between said fixed frequency and said operating frequency. tches.12. The phase-locked loop of claim 11 wherein each of said series of switches are controlled by a corresponding bit of the capacitance selection signal from said calibration circuit.13. The phase-locked loop of claim 1 wherein each of said one or more variable capacitor arrays have capacitances defined by a binary weighting scheme.14. The phase-locked loop of claim 1 wherein each of said one or more variable capacitor arrays have capacitances defined by a unitary weighting scheme wherein each of said variable capacitor arrays have essentially equal capacitances.15. The phase-locked loop of claim 1 wherein said loop filter further comprises one or more resistors manufactured in the same material as said one or more variable capacitor arrays.16. The phase-locked loop of claim 1 wherein said loop filter and said calibration circuit are integrated into a single semiconductor die. d configured to select the second input data signal responsive to the select signal state; a rising edge enable gate coupled to receive at least one of the first input data signal and the second input data signal and configured to generate a first pulse responsive to a first transition edge of the selected first or second input data signal; a first pulse length delay coupled to receive the first pulse from the rising edge enable gate and configured to generate a first pulse loop signal to deactivate the rising edge enable gate responsive to the first pulse; a first falling edge pulse reset control coupled to receive the select signal and configured to select the first input data signal responsive to the select signal state; a second falling edge pulse reset control coupled to receive the select signal and configured to select the second input data signal responsive to the select signal state; a falling edge enable gate coupled to receive the first input data signal and the second input data signal and configured to generate a second pulse responsive to a second transition edge of the selected first or second input data signal; a second pulse length delay coupled to receive the second pulse from the falling edge enable gate and configured to generate a second pulse loop signal to deactivate the falling edge enable gate responsive to the second pulse; and an output coupled to receive the first and second pulses and configured to produce an output of first logic value for the duration of the first pulse, and of second logic value for the duration of the second pulse as the output signal from the multiplexer circuit. 2. The multiplexer circuit of claim 1 further comprising: a first loop keeper coupled to intercept the first pulse loop signal between the first pulse length delay and the rising edge enable gate and configured to deactivate the rising edge enable gate responsive to receiving the first pulse loop signal, thereby blocking subsequent pulse loop signals from reaching the rising edge enable gate; and a reset generator coupled to receive the selected first or second input signal and to output a first reset signal responsive to a falling edge of the selected input signal. 3. The multiplexer circuit of claim 1 further comprising: a second loop keeper circuit coupled to receive the second pulse loop signal from second pulse length delay and configured to deactivate the falling edge enable gate responsive to receiving the second pulse loop signal, thereby blocking subsequent pulse loop front reaching the falling edge enable gate; and a reset generator coupled to receive the selected first or second input signal and to output a second reset signal responsive to a rising edge of the input signal. 4. The multiplexer circuit of claim 1 wherein the output comprises a keeper circuit configured to hold the output signal constant between the first and the second pulses.5. The multiplexer circuit of claim 1 wherein the rising edge enable gate, the falling edge enable gate, and the output are configured to be large devices.6. The multiplexer circuit of claim 1 wherein the width of the first pulse is determined by the amount of delay between the rising edge enable gate producing the first pulse and the first pulse length delay producing the first pulse loop signal.7. The multiplexer circuit of claim 1 wherein the width of the second pulse is determined by the amount of delay between the falling edge enable gate producing the first pulse and the second pulse length delay producing the second pulse loop signal.8. The multiplexer circuit of claim 1 wherein the rising edge enable gate and the falling edge enable gate are configured to receive a level signal from the first input data signal and the second input data signal, and the output is configured to generate a level signal as the output signal.9. A multiplexer circuit for receiving a first input data signal, a second input data signal, a select signal, an