A process is disclosed for manufacturing a lubricant composition comprising combining a superabsorbent polymer with a material for decreasing friction between moving surfaces. The superabsorbent polymer absorbs from about 25 to greater than 100 times its weight in water and may comprise a polymer of
A process is disclosed for manufacturing a lubricant composition comprising combining a superabsorbent polymer with a material for decreasing friction between moving surfaces. The superabsorbent polymer absorbs from about 25 to greater than 100 times its weight in water and may comprise a polymer of acrylic acid, an acrylic ester, acrylonitrile or acrylamide, including co-polymers thereof or starch graft co-polymers thereof or mixtures thereof. A product produced by the process includes the material for decreasing friction comprising a petroleum lubricant containing an additive, water containing an additive, synthetic lubricant, grease, solid lubricant or metal working lubricant, wherein the synthetic lubricant, grease, solid lubricant or metal working lubricant optionally contain an additive. A process comprising controlling the delivery of a lubricant to at least one of two moving surfaces in order to decrease friction between said moving surfaces, is also disclosed. This process includes applying the lubricant composition to at least one of the surfaces. The lubricant composition in this instance comprises a superabsorbent polymer combined with a material for decreasing friction between moving surfaces, wherein the material for decreasing friction comprises a petroleum lubricant, water, synthetic lubricant, grease, solid lubricant or metal working lubricant, and optionally an additive.
대표청구항▼
A process is disclosed for manufacturing a lubricant composition comprising combining a superabsorbent polymer with a material for decreasing friction between moving surfaces. The superabsorbent polymer absorbs from about 25 to greater than 100 times its weight in water and may comprise a polymer of
A process is disclosed for manufacturing a lubricant composition comprising combining a superabsorbent polymer with a material for decreasing friction between moving surfaces. The superabsorbent polymer absorbs from about 25 to greater than 100 times its weight in water and may comprise a polymer of acrylic acid, an acrylic ester, acrylonitrile or acrylamide, including co-polymers thereof or starch graft co-polymers thereof or mixtures thereof. A product produced by the process includes the material for decreasing friction comprising a petroleum lubricant containing an additive, water containing an additive, synthetic lubricant, grease, solid lubricant or metal working lubricant, wherein the synthetic lubricant, grease, solid lubricant or metal working lubricant optionally contain an additive. A process comprising controlling the delivery of a lubricant to at least one of two moving surfaces in order to decrease friction between said moving surfaces, is also disclosed. This process includes applying the lubricant composition to at least one of the surfaces. The lubricant composition in this instance comprises a superabsorbent polymer combined with a material for decreasing friction between moving surfaces, wherein the material for decreasing friction comprises a petroleum lubricant, water, synthetic lubricant, grease, solid lubricant or metal working lubricant, and optionally an additive. e not occupied by said insulator filled STI structure; and performing an anneal procedure at a temperature between about 800 to 1100° C. 2. The method of claim 1, wherein the top portion of said semiconductor substrate is P well region, comprised with P type dopants.3. The method of claim 1, wherein said composite insulator layer is comprised of an underlying pad silicon dioxide layer at a thickness between about 50 to 200 Angstroms, and an overlying silicon nitride layer at a thickness between about 1000 to 3000 Angstroms.4. The method of claim 1, wherein said shallow trench shape is formed in the top portion of said semiconductor substrate via a reactive ion etching (RIE), procedure, using Cl2or SF6as an etchant for the semiconductor material.5. The method of claim 1, wherein the depth of said shallow trench shape in the top portion of said semiconductor substrate, is between about 3000 to 5000 Angstroms.6. The method of claim 1, wherein the sides of said shallow trench shape are formed with a taper between about 75 to 90° with reference to the horizontal top surface of said shallow trench shape.7. The method of claim 1, wherein said rounded corners, located at the bottom of said shallow trench shape, are formed via thermal growth of a silicon dioxide layer on the exposed surfaces of said shallow trench shape at a thickness between about 50 to 200 Angstroms, via a thermal oxidation procedure performed at a temperature between about 800 to 1200° C. in an oxygen—steam ambient, followed by removal of the thermally grown silicon dioxide layer using dilute hydrofluoric acid as an etchant.8. The method of claim 1, wherein said group of insulator liner layers is comprised of an underlying, first composite insulator layer, and an overlying, second composite insulator layer.9. The method of claim 1, wherein said group of insulator liner layers is obtained via atomic layer deposition (ALD), procedures, performed at a temperature between about 25 to 400° C.10. The method of claim 8, wherein said underlying, first composite insulator layer is comprised with an underlying, silicon oxide layer grown to a thickness between about 5 to 10 Angstroms, using silane and nitrous oxide as reactants.11. The method of claim 8, wherein said underlying, first composite insulator layer is comprised with an overlying, silicon nitride layer grown to a thickness between about 5 to 10 Angstroms, using silane and ammonia as reactants.12. The method of claim 8, wherein said overlying, second composite insulator layer is comprised with an underlying, silicon oxide layer grown to a thickness between about 5 to 10 Angstroms, using silane and nitrous oxide as reactants.13. The method of claim 8, wherein said overlying, second composite insulator layer is comprised with an overlying, silicon nitride layer grown to a thickness between about 5 to 10 Angstroms, using silane and ammonia as reactants.14. The method of claim 1, wherein said insulator shape located in said shallow trench shape, is comprised of silicon oxide, obtained via high density plasma (HDP), procedures, at a thickness between about 5000 to 8000 Angstroms.15. The method of claim 1, wherein removal of said group of insulator liner layers from top surface of portions of said semiconductor substrate not occupied by said insulator filled STI structure, is accomplished via a chemical mechanical polishing (CMP), procedure.16. A method of forming a shallow trench isolation (STI), structure in a semiconductor substrate, featuring a group of insulator liner layers located on the surfaces of a shallow trench shape that is used to accommodate the STI structure, comprising the steps of: forming a well region in a top portion of said semiconductor substrate; forming a composite insulator layer on said semiconductor substrate, comprised of an underlying, first silicon dioxide layer and an overlying, first silicon nitride layer; forming an shallow trench shape in a composite insulator layer and in a top portion of said well region; growing a second silicon dioxide layer on the exposed surfaces of said shallow trench shape; removing said second silicon dioxide layer resulting in rounded corners at the bottom of said shallow trench shape; depositing said group of insulator liner layers on exposed surfaces of said shallow trench shape, with said group of insulator layers comprised of an underlying, first silicon oxide layer, a second silicon nitride layer, a second silicon oxide layer, and an overlying, third silicon nitride layer; depositing a third silicon oxide layer completely filling said shallow trench shape; performing a planarization procedure resulting in an insulator filled, STI structure in said shallow trench shape; performing a post-planarization anneal procedure at a temperature between about 800 to 1000° C.; and removing portions of said group of insulator liner layers, and removing said composite insulator layer, from top surface of portions of said semiconductor substrate not occupied by said insulator filled STI structure. 17. The method of claim 16, wherein said well region is a P well region, formed in a top portion of said semiconductor substrate via implantation of boron or BF2ions, at an energy between about 100 to 500 KeV, and at a dose between about 1E12 to 1E13 atoms/cm2.18. The method of claim 16, wherein said shallow trench shape is formed in the top portion of said well region via a reactive ion etching (RIE), procedure, using Cl2or SF6as an etchant for the semiconductor material.19. The method of claim 16, wherein the depth of said shallow trench shape, in the top portion of said well region, is between about 3000 to 5000 Angstroms.20. The method of claim 16, wherein the sides of said shallow trench shape are formed with a taper between about 75 to 90°, with reference to a horizontal top surface of said shallow trench shape.21. The method of claim 16, wherein said second silicon dioxide layer is obtained at a thickness between about 50 to 200 Angstroms, via a thermal oxidation procedure performed at a temperature between about 800 to 1200° C., in an oxygen—steam ambient.22. The method of claim 16, wherein said second silicon dioxide layer is removed via a wet etch procedure using dilute hydrofluoric acid.23. The method of claim 16, wherein said first silicon oxide layer of said group of insulator liner layers, is obtained at a thickness between about 5 to 10 Angstroms, via atomic layer deposition (ALD), procedures, performed at a temperature between about 25 to 400° C., using silane and nitrous oxide as reactants.24. The method of claim 16, wherein said second silicon nitride layer of said group of insulator liner layers, is obtained at a thickness between about 5 to 10 Angstroms, via ALD procedures, performed at a temperature between about 25 to 400° C., using silane and ammonia as reactants.25. The method of claim 16, wherein said second silicon oxide layer of said group of insulator liner layers, is obtained at a thickness between about 5 to 10 Angstroms, via ALD procedures, performed at a temperature between about 25 to 400° C., using silane and nitrous oxide as reactants.26. The method of claim 16, wherein said third silicon nitride layer of said group of insulator liner layers, is obtained at a thickness between about 5 to 10 Angstroms, via ALD procedures, performed at a temperature between about 25 to 400° C., using silane and ammonia as reactants.27. The method of claim 16, wherein said third silicon oxide layer, used to completely fill said shallow trench shape, is obtained at a thickness between about 5000 to 8000 Angstroms, via high density plasma (HDP), procedures.28. The method of claim 16, wherein said planarization procedure is a chemical mechanical polishing procedure.
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