초록 ▼

The value of non-discrete metric variables are synchronized at the processor level. When the profiler requests metric information for non-discrete metric variables, the operating system kernel obtains a global value for the requested metric rather than obtaining per-processor metric values for each

The value of non-discrete metric variables are synchronized at the processor level. When the profiler requests metric information for non-discrete metric variables, the operating system kernel obtains a global value for the requested metric rather than obtaining per-processor metric values for each processor. The global value may be written to trace records. By using a single global per-processor metric for all processors, a single global value of the last metric variable may be used for calculating the resources consumed on all processors since a last recorded event.

대표청구항 ▼

The value of non-discrete metric variables are synchronized at the processor level. When the profiler requests metric information for non-discrete metric variables, the operating system kernel obtains a global value for the requested metric rather than obtaining per-processor metric values for each

The value of non-discrete metric variables are synchronized at the processor level. When the profiler requests metric information for non-discrete metric variables, the operating system kernel obtains a global value for the requested metric rather than obtaining per-processor metric values for each processor. The global value may be written to trace records. By using a single global per-processor metric for all processors, a single global value of the last metric variable may be used for calculating the resources consumed on all processors since a last recorded event. d second metal patterns is smaller than a minimum size of the second via patterns; (l) after the step (k), extracting a fourth area where the second metal patterns and the third metal patterns do not exist; (m) placing a plurality of additional second via patterns each having a minimum size with a minimum pitch in the fourth area; (n) deleting the additional second via pattern which do not meet a minimum allowable distance between the second metal patterns and the second via patterns positioned in the step (i); (o) positioning an additional third metal pattern to completely cover the additional second via pattern; and (p) deleting the additional third metal pattern which do not meet a minimum allowable distance between the third metal patterns. 5. A method of fabricating a semiconductor device comprising the steps of: (a) positioning a plurality of first metal interconnection patterns, a plurality of first via patterns and a plurality of second metal interconnection patterns in such a way that each of antenna ratios of the first metal patterns, the first via patterns and the second metal patterns becomes equal to or smaller than an allowable antenna ratio; (b) broadening a width of each of the first metal patterns by a minimum line width of the first metal patterns; (c) connecting the broadened first metal patterns at a first area where a distance between the broadened first metal patterns is smaller than a minimum size of the first via patterns; (d) after the step (c), extracting a second area where the first metal patterns and the second metal patterns do not exist; (e) positioning an additional first metal pattern to completely cover the second area; (f) deleting a portion of the additional first metal pattern which do not meet a minimum allowable distance between the first metal patterns positioned in the step (a); (g) placing a plurality of additional first via patterns each having a minimum size with a minimum pitch in an area where the additional first metal pattern is positioned; and (h) deleting the additional first via pattern which do not meet a minimum allowable distance between the first metal patterns and the first via patterns positioned in the step (a). 6. A method of fabricating a semiconductor device according to claim 5, further comprising the steps of: (i) positioning a plurality of third metal interconnection patterns, a plurality of second via patterns and the second metal patterns in such a way that each of antenna ratios of the third metal patterns, the second via patterns and the second metal patterns becomes equal to or smaller than an allowable antenna ratio; (j) broadening a width of each of the second metal patterns by a minimum line width of the second metal patterns; (k) connecting the broadened second metal patterns at a third area where a distance between the broadened second metal patterns is smaller than a minimum size of the second via patterns; (l) after the step (k), extracting a fourth area where the second metal patterns positioned in the step (i) and the third metal patterns positioned in the step (i) do not exist; (m) positioning an additional second metal pattern to completely cover the fourth area; (n) deleting a portion of the additional second metal pattern which do not meet a minimum allowable distance between the second metal patterns positioned in the step (i); (o) placing a plurality of additional second via patterns each having a minimum size with a minimum pitch in an area where the additional second metal pattern is positioned; and (p) deleting the additional second via pattern which do not meet a minimum allowable distance between the second metal patterns and the second via patterns positioned in the step (i). 7. A method of fabricating a semiconductor device according to claim 5, further comprising the steps of: (i) positioning an additional second metal pattern to completely cover the additional first via pa ttern; and (j) deleting the additional second metal pattern which do not meet a minimum allowable distance between the second metal patterns positioned in the step (a). 8. A method of fabricating a semiconductor device according to claim 7, further comprising the steps of: (k) positioning a plurality of third metal interconnection patterns, a plurality of second via patterns and the second metal patterns in such a way that each of antenna ratios of the third metal patterns, the second via patterns and the second metal patterns becomes equal to or smaller than an allowable antenna ratio; (l) broadening a width of each of the second metal patterns by a minimum line width of the second metal patterns; (m) connecting the broadened second metal patterns at a third area where a distance between the broadened second metal patterns is smaller than a minimum size of the second via patterns; (n) after the step (m), extracting a fourth area where the second metal patterns and the third metal patterns do not exist; (o) positioning an extra additional second metal pattern to completely cover the fourth area; (p) deleting a portion of the extra additional second metal pattern which do not meet a minimum allowable distance between the second metal patterns positioned in the step (k); (q) placing a plurality of additional second via patterns each having a minimum size with a minimum pitch in an area where the extra additional second metal pattern is positioned; (r) deleting the additional second via pattern which do not meet a minimum allowable distance between the second metal patterns and the second via patterns positioned in the step (k); (s) positioning an additional third metal pattern to completely cover the additional second via pattern; and (t) deleting the additional third metal pattern which do not meet a minimum allowable distance between the third metal patterns positioned in the step (k). 9. A method of fabricating a semiconductor device comprising the steps of: (a) positioning a plurality of first metal interconnection patterns, a plurality of first via patterns and a plurality of second metal interconnection patterns in such a way that each of antenna ratios of the first metal patterns, the first via patterns and the second metal patterns becomes equal to or smaller than an allowable antenna ratio; (b) broadening a width of each of the first metal patterns by a minimum line width of the first metal patterns; (c) connecting the broadened first metal patterns at a first area where a distance between the broadened first metal patterns is smaller than a minimum size of the first via patterns; (d) after the step (c), extracting a second area where the first metal patterns and the second metal patterns do not exist; (e) positioning a plurality of additional first metal patterns each having a minimum size with a minimum pitch in a form of dots in the second area; (f) deleting a portion of the additional first metal patterns which do not meet a minimum allowable distance between the first metal patterns positioned in the step (a); (g) placing an additional first via patterns each having a minimum size in an area where the additional first metal patterns are positioned; and (h) deleting the additional first via pattern which do not meet a minimum allowable distance between the first metal patterns and the first via patterns positioned in the step (a). 10. A method of fabricating a semiconductor device according to claim 9, further comprising the steps of: (i) positioning a plurality of third metal interconnection patterns, a plurality of second via patterns and the second metal patterns in such a way that each of antenna ratios of the third metal patterns, the second via patterns and the second metal patterns becomes equal to or smaller than an allowable antenna ratio; (j) broadening a width of each of the second metal patterns by a minimum line width of the second metal patte