Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/4763
H01L-021/44
H01L-021/302
출원번호
US-0661735
(2000-09-14)
발명자
/ 주소
Houston, Theodore W.
Joyner, Keith A.
출원인 / 주소
Texas Instruments Incorporated
대리인 / 주소
Tung, Yingsheng
인용정보
피인용 횟수 :
171인용 특허 :
5
초록▼
A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain regions (13-14, 316-318, 321-323). A gate section (21) projects upwardly from between an adjacent pair of these regions, into an insulating
A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain regions (13-14, 316-318, 321-323). A gate section (21) projects upwardly from between an adjacent pair of these regions, into an insulating layer (46, 363). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (51), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (56-57) on opposite sides of and immediately adjacent the gate section. A conductive layer (61, 120) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections. The portion of the conductive material remaining in each recess is self-aligned to be immediately adjacent at least one gate section, and serves as a local interconnect for a respective source or drain region.
대표청구항▼
A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain regions (13-14, 316-318, 321-323). A gate section (21) projects upwardly from between an adjacent pair of these regions, into an insulating
A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain regions (13-14, 316-318, 321-323). A gate section (21) projects upwardly from between an adjacent pair of these regions, into an insulating layer (46, 363). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (51), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (56-57) on opposite sides of and immediately adjacent the gate section. A conductive layer (61, 120) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections. The portion of the conductive material remaining in each recess is self-aligned to be immediately adjacent at least one gate section, and serves as a local interconnect for a respective source or drain region. a first temperature in a water vapor preparing unit; (d) keeping the thus synthesized water vapor in a gaseous state and transferring it to a wafer heat treatment chamber where the wafer has been placed, to form a water vapor and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the refractory metal; (e) heat treating the first main surface having the metal gate electrode formed thereover at a second temperature higher than the first temperature in the water-vapor- and hydrogen-containing gas atmosphere in the wafer heat treatment chamber, thereby repairing defects in the gate insulating film right under the metal gate electrode. 6. A process according to claim 5, wherein the refractory metal is molybdenum or tungsten.7. A process according to claim 6, wherein the water-vapor- and hydrogen-containing gas further contains a nitrogen or ammonia gas.8. A process for manufacturing a semiconductor integrated circuit device, which comprises the steps of: (a) forming, over the silicon surface on a first main surface of a wafer, a gate insulating film having an effective film thickness less than 5 nm in terms of SiO 2and made of a single insulating film containing as a principal component a metal oxide having a dielectric constant larger than silicon dioxide or a composite film thereof with another insulating film; (b) forming, over the gate insulating film, a metal film having a refractory metal as a principal component without disposing, therebetween, an intermediate layer containing polycrystalline silicon as a principal component and then patterning the metal film to form a metal gate electrode; (c) after step (b), synthesizing water vapor from a mixed gas containing oxygen and hydrogen gases by use of a catalyst at a first temperature in a water vapor preparing unit; (d) keeping the thus synthesized water vapor in a gaseous state and transferring it to a wafer heat treatment chamber where the wafer has been placed, to form a water vapor and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the refractory metal; (e) heat treating the first main surface having the metal gate electrode formed thereover at a second temperature higher than the first temperature in the water-vapor- and hydrogen-containing gas atmosphere in the wafer heat treatment chamber, thereby repairing the defects in the gate insulating film right under the metal gate electrode. 9. A process according to claim 8, wherein the metal constituting the metal oxide film is titanium, zirconium or hafnium.10. A process according to claim 8, wherein the metal constituting the metal oxide film is tantalum.11. A process according to claim 8, wherein the metal constituting the metal oxide film is aluminum.12. A process according to claim 8, wherein the metal oxide film is a high dielectric substance including a ABO3type average perovskite structure and is in a paraelectric phase at an operating temperature.13. A process according to claim 12, wherein the high dielectric substance is BST.14. A process for manufacturing a semiconductor integrated circuit device, which comprises the steps of: (a) forming, over the silicon surface on a first main surface of a wafer, a gate insulating film containing, as a principal component, an oxide of a first refractory metal having a redox equilibrium curve in a water-vapor- and hydrogen-containing gas atmosphere on the lower water vapor side than that of silicon, the gate insulating film having defects which include oxygen deficient first refractory metal; (b) heat treating the first main surface having the gate insulating film formed thereover in a water-vapor- and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxida
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Kornachuk, Stephen; Mali, Jim; Lambert, Carole; Becker, Scott T., Enforcement of semiconductor structure regularity for localized transistors and interconnect.
Kornachuk, Stephen; Mali, Jim; Lambert, Carole; Becker, Scott T., Enforcement of semiconductor structure regularity for localized transistors and interconnect.
Kornachuk, Stephen; Mali, Jim; Lambert, Carole; Becker, Scott T., Enforcement of semiconductor structure regularity for localized transistors and interconnect.
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Becker, Scott T.; Smayling, Michael C., Integrated circuit device with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level.
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Becker, Scott T.; Smayling, Michael C., Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion.
Becker, Scott T.; Smayling, Michael C., Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends.
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Becker, Scott T.; Smayling, Michael C., Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two different extension distances beyond conductive contacting structures.
Becker, Scott T.; Smayling, Michael C., Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two linear-shaped conductive structures of different length.
Becker, Scott T.; Smayling, Michael C., Integrated circuit including at least three linear-shaped conductive structures at equal pitch including linear-shaped conductive structure having non-gate portion length greater than gate portion length.
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Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels.
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Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature.
Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer.
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Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships.
Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer.
Becker, Scott T., Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications.
Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications.
Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications.
Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications.
Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications.
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Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature.
Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer.
Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer.
Becker, Scott T., Integrated circuit including cross-coupled transistors having two complementary pairs of co-aligned gate electrodes with offset contacting structures positioned between transistors of different type.
Becker, Scott T., Integrated circuit including cross-coupled transistors with two transistors of different type formed by same gate level structure and two transistors of different type formed by separate gate level structures.
Becker, Scott T., Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature.
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Becker, Scott T.; Smayling, Michael C., Integrated circuit including gate electrode level region including at least four linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type.
Becker, Scott T.; Smayling, Michael C., Integrated circuit including gate electrode level region including at least seven linear-shaped conductive structures of equal length positioned at equal pitch with at least two linear-shaped conductive structures each forming one transistor and having extending portion sized greater than gate portion.
Becker, Scott T.; Smayling, Michael C., Integrated circuit including gate electrode level region including at least three linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type.
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Becker, Scott T.; Smayling, Michael C., Integrated circuit including linear gate electrode structures having different extension distances beyond contact.
Becker, Scott T.; Smayling, Michael C., Integrated circuit including linear-shaped conductive structures that have gate portions and extending portions of different size.
Becker, Scott T.; Smayling, Michael C., Integrated circuit with gate electrode level including at least four linear-shaped conductive structures of equal length and equal pitch with linear-shaped conductive structure forming one transistor.
Becker, Scott T.; Smayling, Michael C., Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset ends.
Becker, Scott T.; Smayling, Michael C., Integrated circuit with gate electrode level region including at least four linear-shaped conductive structures forming gate electrodes of transistors and including extending portions of at least two different sizes.
Becker, Scott T.; Smayling, Michael C., Integrated circuit with gate electrode level region including multiple linear-shaped conductive structures forming gate electrodes of transistors and including uniformity extending portions of different size.
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Becker, Scott T.; Smayling, Michael C., Method for fabricating integrated circuit having at least three linear-shaped gate electrode level conductive features of equal length positioned side-by-side at equal pitch.
Becker, Scott T.; Smayling, Michael C., Method for fabricating integrated circuit having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch.
Becker, Scott T.; Smayling, Michael C., Method for fabricating integrated circuit including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear condcutive segment.
Becker, Scott T.; Smayling, Michael C., Method for fabricating integrated circuit with gate electrode level portion including at least two complementary transistor forming linear conductive segments and at least one non-gate linear conductive segment.
Becker, Scott T.; Smayling, Michael C., Method for fabricating integrated circuit with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level.
Becker, Scott T.; Smayling, Michael C., Method of fabricating integrated circuit including at least six linear-shaped conductive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length.
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Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.
Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.
Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.
Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.
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Becker, Scott T.; Smayling, Michael C., Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid.
Becker, Scott T.; Smayling, Michael C., Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid.
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Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods.
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Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same.
Becker, Scott T.; Smayling, Michael C., Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same.
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Becker, Scott T.; Smayling, Michael C., Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same.
Becker, Scott T.; Smayling, Michael C., Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods.
Becker, Scott T.; Smayling, Michael C., Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect level.
Becker, Scott T.; Smayling, Michael C., Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or ground.
Becker, Scott T.; Smayling, Michael C., Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch.
Becker, Scott T.; Smayling, Michael C., Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengths.
Becker, Scott T.; Smayling, Michael C., Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common type on equal pitch.
Becker, Scott T.; Smayling, Michael C., Semiconductor device including at least six transistor forming linear shapes including at least two different gate contact connection distances.
Becker, Scott T.; Smayling, Michael C., Semiconductor device including at least six transistor forming linear shapes including at least two transistor forming linear shapes having different extension distances beyond gate contact.
Becker, Scott T.; Smayling, Michael C., Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends.
Becker, Scott T.; Smayling, Michael C., Semiconductor device including transistor forming linear shapes including gate portions and extending portions of different size.
Becker, Scott T.; Smayling, Michael C., Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length.
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Becker, Scott T.; Smayling, Michael C., Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos.
Becker, Scott T.; Smayling, Michael C., Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region and having at least two gate contacts positioned outside separating non-diffusion region.
Becker, Scott T.; Smayling, Michael C., Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region.
Becker, Scott T.; Smayling, Michael C., Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different length.
Becker, Scott T.; Smayling, Michael C., Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction.
Becker, Scott T.; Smayling, Michael C., Semiconductor device with linearly restricted gate level region including four serially connected transistors of first type and four serially connected transistors of second type separated by non-diffusion region.
Becker, Scott T.; Smayling, Michael C., Semiconductor device with linearly restricted gate level region including four transistors of first type and four transistors of second type with gate defining shapes of different length.
Becker, Scott T.; Smayling, Michael C., Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contacts.
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