초록 ▼

A hybrid access terminal is a Wireless Communication Device (WCD) capable of operating over different types of communication networks. An exemplary WCD operates on both IS-2000 and IS-856 networks, and is capable of inter-system handoffs between these two types of networks. Such capabilities enable

A hybrid access terminal is a Wireless Communication Device (WCD) capable of operating over different types of communication networks. An exemplary WCD operates on both IS-2000 and IS-856 networks, and is capable of inter-system handoffs between these two types of networks. Such capabilities enable the exemplary WCD to provide voice, data and short messaging services on IS-2000 networks, and also to provide high speed packet data service on IS-856 networks. A method of operating on different networks includes establishing a data session on the first network, detecting a request for a packet data service, handing-off the data session to a second network, detecting a dormancy of the data session, transitioning to a dormant state and initiating a Dormancy time-out period when the dormancy is detected, and monitoring both the first network and the second network for paging messages while in the dormant state.

대표청구항 ▼

A hybrid access terminal is a Wireless Communication Device (WCD) capable of operating over different types of communication networks. An exemplary WCD operates on both IS-2000 and IS-856 networks, and is capable of inter-system handoffs between these two types of networks. Such capabilities enable

A hybrid access terminal is a Wireless Communication Device (WCD) capable of operating over different types of communication networks. An exemplary WCD operates on both IS-2000 and IS-856 networks, and is capable of inter-system handoffs between these two types of networks. Such capabilities enable the exemplary WCD to provide voice, data and short messaging services on IS-2000 networks, and also to provide high speed packet data service on IS-856 networks. A method of operating on different networks includes establishing a data session on the first network, detecting a request for a packet data service, handing-off the data session to a second network, detecting a dormancy of the data session, transitioning to a dormant state and initiating a Dormancy time-out period when the dormancy is detected, and monitoring both the first network and the second network for paging messages while in the dormant state. ical component comprises a servo unit.10. The optical memory apparatus of claim 1, wherein said photo-detector comprises a first photo-detector element receiving and detecting a data signal component, and a second photo-detector element receiving and detecting a servo signal component.11. The optical memory apparatus of claim 1, wherein: said base further comprises a unitary and integral, second recess and an eject motor mounted within said unitary and integral, second recess. 12. The optical memory apparatus of claim 11, wherein: said base has a medium holding portion which receives and holds an optical memory medium; and the first and second unitary and integral recesses of said base are displaced from the medium holding portion. olar transistor, and a base of said first bipolar transistor; a coupling between an emitter of said first bipolar transistor and a ground potential; and a coupling from an emitter of said second bipolar transistor through the second resistive element to a ground potential. 6. The reference circuit of claim 1, wherein a first current which flows from the input power source through said second field effect transistor and said first resistive element to a ground potential decreases as the temperature of said first subcircuit increases.7. The reference circuit of claim 1, wherein a second current which flows from the input power source through said second bipolar transistor and said second resistive element to a ground potential increases as the temperature of said second subcircuit increases.8. The reference circuit of claim 1, wherein said first and second resistive elements have positive thermal coefficients.9. A memory device comprising: a memory array; a control circuit; an input/output circuit; and a reference circuit for supplying power to the memory array, the control circuit, and the input/output circuit, said reference circuit further comprising, a first subcircuit, comprising:a first current mirror having a first input node and a first output node, said first input node coupled to an input power source;a first field effect transistor, coupled a first leg of the first current mirror; anda second field effect transistor, coupled to a second leg of the first current mirror and to a first resistive element:wherein said first subcircuit produces a first output voltage at the first output node, said first output voltage being a function of a first threshold voltage of the first field effect transistor, a second threshold voltage of the second field effect transistor, and a first resistance of the first resistive element which is a function of a first temperature of the first subcircuit;a second subcircuit, comprising:a second current mirror having a second input node and a second outputa first bipolar transistor, coupled to a first leg of the second current mirror; anda second bipolar transistor, coupled to a second leg of the second current mirror and to a second resistive element;wherein said second subcircuit produces a second output voltage at the a second output node, said second output voltage being a function of a first base-to-emitter voltage of the a first bipolar transistor, a second base-to-emitter voltage of the second bipolar transistor, and a second resistance of the second resistive element which is a function of a second temperature of the second subcircuit;a summing circuit including a first control terminal coupled to said first node and a second control terminal coupled to said second node, for producing a summed power signal; andan output circuit for outputting said summed power signal.10. The memory device of claim 9, further comprising: coupling between a gate of said first field effect transistor, a gate of said second field effect transistor, and a drain of said first field effect transistor; coupling between a source of said first field effect transistor and a ground potential; and a coupling from a source of said second field effect transistor through the first resistive element to a ground potential. 11. The memory device of claim 10, wherein said first current mirror comprises: a first transistor having a source coupled to the input power source and a drain coupled to the drain of said first field effect transistor; and a second transistor having a source coupled to the input power source and a drain coupled to the drain of said second field effect transistor. 12. The memory device of claim 11, wherein said first and second transistors are PMOS transistors.13. The memory device of claim 9, further comprising: a coupling between a gate of first bipolar transistor, a gate of said second bipolar transistor, and a base of said first bipolar transistor; a coupling bet ween an emitter of said first bipolar transistor and a ground potential; and a coupling from an emitter of said second bipolar transistor through the second resistive element to a ground potential. 14. The memory device of claim 9, wherein a first current which flows from the input power source through said second field effect transistor and said first resistive element to a ground potential decreases as the temperature of said first subcircuit increases.15. The memory device of claim 9, wherein a second current which flows from the input power source through said second bipolar transistor and said second resistive element to a ground potential increases as the temperature of said second subcircuit increases.16. The memory device of claim 9, wherein said first and second resistive elements have positive thermal coefficients.17. A processor based system comprising: a bus; a processor, coupled to said bus; an input/output device, coupled to said bus; a memory, coupled to said bus; wherein said memory include a reference circuit, said reference circuit further comprising, a first subcircuit, comprising:a first current mirror having a first input node and a first output node, said first input node coupled to an input power source;a first field effect transistor, coupled a first leg of the first current mirror; anda second field effect transistor, coupled a second leg of the first current mirror and to a first resistive element;wherein said first subcircuit produces a first output voltage at the first output node, said first output voltage being a function of a first threshold voltage of the first field effect transistor, a second threshold voltage of the second field effect transistor, and a first resistance of the first resistive element which is a function of a first temperature of the first subcircuit;a second subcircuit, comprising:a second current mirror having a second input node and a second output node, said second input node coupled to the input power source;a first bipolar transistor, coupled a first leg of the second current mirror; anda second bipolar transistor, coupled a second leg of the second current mirror and to a second resistive element;wherein said second subcircuit produces a second output voltage at the second output node, said second output voltage being a function of a first base-to-emitter voltage of the first bipolar transistor, a second base-to-emitter voltage of the second bipolar transistor, and a second resistance of the second resistive element which is a function of a second temperature of the second subcircuit;a summing circuit including a first control terminal coupled to said first node and a second control terminal coupled to said second node, for producing a summed power signal; andan output circuit for outputting said summed power signal.18. The processor based system of claim 17, further comprising: a coupling between a gate of said first field effect transistor, a gate of said second field effect transistor, and a drain of said first field effect transistor; a coupling between a source of said first field effect transistor and a ground potential; and a coupling from a source of said second field effect transistor through the first resistive element to a ground potential. 19. The processor based system of claim 18, wherein said first current mirror comprises: a first transistor having a source coupled to the input power source and a drain coupled to the drain of said first field effect transistor; and a second transistor having a source coupled to the input power source and a drain coupled to the drain of said second field effect transistor. 20. The processor based system of claim 19, wherein said first and second transistors are PMOS transistors.21. The processor based system of claim 17, further comprising: a coupling between a gate of first bipolar transistor, a gate of said second bipolar transistor, and a base of said first bipolar transistor; a coup