초록
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Embodiments of methods, communication devices, communication systems, and computer program products may facilitate communication of information via a frame-check sequence that has an information block associated therewith. For example, one or more information blocks may be provided and respectively associated with one or more information block frame-check sequences. A message for transmission may be provided and a message frame-check sequence may be computed based on the message. One of the information blocks may also be selected for transmission along w...
Embodiments of methods, communication devices, communication systems, and computer program products may facilitate communication of information via a frame-check sequence that has an information block associated therewith. For example, one or more information blocks may be provided and respectively associated with one or more information block frame-check sequences. A message for transmission may be provided and a message frame-check sequence may be computed based on the message. One of the information blocks may also be selected for transmission along with the message. Rather than constructing a packet that includes both the selected information block and the message, however, the information block frame-check sequence that is associated with the selected information block is added to the message frame-check sequence to compute a transmit frame-check sequence. A packet comprising the message and the transmit frame-check sequence may then be transmitted. Once received, the packet may be divided by a generator polynomial to determine whether any remainder results. If the remainder is non-zero, then a determination may be made whether remainder corresponds to any of the one or more information block frame-check sequences. If the remainder does correspond to one of the information block frame-check sequences, then the information block associated with the information block frame-check sequence that corresponds to the remainder may be processed as received information.
대표
청구항
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Embodiments of methods, communication devices, communication systems, and computer program products may facilitate communication of information via a frame-check sequence that has an information block associated therewith. For example, one or more information blocks may be provided and respectively associated with one or more information block frame-check sequences. A message for transmission may be provided and a message frame-check sequence may be computed based on the message. One of the information blocks may also be selected for transmission along w...
Embodiments of methods, communication devices, communication systems, and computer program products may facilitate communication of information via a frame-check sequence that has an information block associated therewith. For example, one or more information blocks may be provided and respectively associated with one or more information block frame-check sequences. A message for transmission may be provided and a message frame-check sequence may be computed based on the message. One of the information blocks may also be selected for transmission along with the message. Rather than constructing a packet that includes both the selected information block and the message, however, the information block frame-check sequence that is associated with the selected information block is added to the message frame-check sequence to compute a transmit frame-check sequence. A packet comprising the message and the transmit frame-check sequence may then be transmitted. Once received, the packet may be divided by a generator polynomial to determine whether any remainder results. If the remainder is non-zero, then a determination may be made whether remainder corresponds to any of the one or more information block frame-check sequences. If the remainder does correspond to one of the information block frame-check sequences, then the information block associated with the information block frame-check sequence that corresponds to the remainder may be processed as received information. ance, operand data from the memory before the load instruction to load the operand data read from the memory is issued, and a read ahead controller for the register which reads, in advance, the operand data from the register before the load instruction to load the operand data read from the register is issued. 3. A data processing system according to claim 2, further comprising: a first dedicated bus connecting the read ahead controller for the memory and the memory, and a second dedicated bus connecting the read ahead controller for the register and the register. 4. A data processing system according to claim 1, wherein both the processing unit and the read ahead control unit are packaged in a LSI package.5. A data processing system according to claim 1, wherein the read ahead control unit comprises: an address register that designates an address of the memory or the register at which read ahead is to be performed, and a data register that stores operand data read, in advance, from the memory and the register. 6. A data processing system according to claim 5, wherein the said read ahead control unit further comprises: an address register valid flag that indicates validity of the address that the address register designates, and a data register valid flag that indicates validity of the operand data stored in the data register, and wherein the read ahead control unit writes operand data read from the memory and the register when the data register validity flag is set, and the read ahead control unit does not write operand data read from the memory and the register when the data register validity flag is not set. 7. A data processing system according to claim 6, further comprising. a counter circuit for measuring time while the address register valid flag is set, and wherein when the address register valid flag is set for a time larger than predetermined time out value, both the address register valid flag and the data register valid flag are reset. 8. A data processing system comprising: a processing unit for executing a program; a memory for storing operand data associated with the program; a register for storing operand data associated with the program; and a memory access control unit connected to the processing unit, the memory and the register via a bus, for reading the operand data from the memory and the register in response to a store instruction from the processing unit and before the program requests the operand data from the memory and the register, wherein the processing unit, prior to requesting the operand data, continues execution of the program while said memory access control unit reads the operand data from the memory and the register. 9. A data processing system according to claim 8, wherein the memory access control unit further comprises: a memory access controller for the memory which reads, in advance, operand data from the memory before the program requests the operand data read from the memory, and a memory access controller for the register which reads, in advance, operand data from the register before the program requests the operand data read from the register. 10. A data processing system according to claim 8, further comprising: a first dedicated bus connecting the memory access controller for the memory and the memory, and a second dedicated bus connecting the memory access controller for the register and the register. 11. A data processing system according to claim 8, wherein both the processing unit and the memory access control unit are packaged in a LSI package.12. A data processing system according to claim 8, wherein the memory access control unit comprises: an address register that designates an address of the memory or the register at which read ahead is to be performed, and a data register that stores operand data read, in advance, from the memory and the register. 13. A data processing system according to claim 12, wherein the s aid read ahead control unit further comprises: an address register valid flag that indicates validity of the address that the address register designates, and a data register valid flag that indicates validity of the operand data stored in the data register, and wherein the memory access control unit writes operand data read from the memory and the register when the data register validity flag is set, and the memory access control unit does not write operand data read from the memory and the register when the data register validity flag is not set. 14. A data processing system according to claim 13, further comprising a counter circuit for measuring time while the address register valid flag is set, and wherein when the address register valid flag is set for a time larger than predetermined time out value, both the address register valid flag and the data register valid flag are reset. 15. A memory access controller comprising: a bus controller for controlling an external bus for connecting to a processing unit which executes instruction codes; an interface unit for connecting an external memory and an external register, both the external memory and the external register storing operand data associated with the instruction codes; and a read ahead control unit connected to the bus controller and the interface unit, for reading, in advance, operand data from the external memory and the external register in response to a store instruction from the processing unit and before loading the operand data to the processing unit from the external memory and the external register in response to a load instruction from the processing unit, wherein the processing unit, prior to issuing the load instruction, executes other instruction codes while said read ahead control unit reads the operand data from the external memory and the external register. 16. A memory access controller according to claim 15, wherein the read ahead control unit further comprises: a read ahead controller for the external memory which reads, in advance, operand data from the external memory before the load instruction to load the operand data read from the external memory is issued, and a read ahead controller for the external register which reads, in advance, the operand data from the external register before instruction to load the operand data read from the external register is issued. 17. A memory access controller comprising: a bus controller for controlling an external bus for connecting to a processing unit which executes a program; an interface unit for connecting an external memory and an external register, both the external memory and the external register storing operand data associated with the instruction codes; and a read ahead control unit connected to the bus controller and the interface unit, for reading, in advance, operand data from the external memory and the external register in response to a store instruction from the processing unit and before the program requests the operand data from the external memory and the external register, wherein the processing unit, prior to requesting the operand data, continues execution while said read ahead control unit reads the operand data from the external memory and the external register. 18. A memory access controller according to claim 17, wherein the read ahead control unit further comprises: a read ahead controller for the external memory which reads, in advance, operand data from the external memory before the program requests the operand data read from the external memory, and a read ahead controller for the external register which reads, in advance, operand data from the external register before the program requests the operand data read from the external register. 19. A data processing system comprising: a processing unit for executing instruction codes; an interface unit for connecting an external memory and an external register, both the external memo ry and the external register storing operand data associated with the instruction codes; and a read ahead control unit connected to the bus controller and the interface unit, for reading, in advance, operand data from the external memory and the external register in response to a store instruction from the processing unit and before loading the operand data to the processing unit from the external memory and the external register in response to a load instruction from the processing unit, wherein the processing unit, prior to issuing the load instruction, executes other instruction codes while said read ahead control unit reads the operand data from the external memory and the external register. 20. A memory access controller comprising: a processing unit for executing a program; an interface unit for connecting an external memory and an external register, both the external memory and the external register storing operand data associated with the instruction codes; and a read ahead control unit connected to the bus controller and the interface unit, for reading, in advance, operand data from the external memory and the external register in response to a store instruction from the processing unit and before the program requests the operand data from the external memory and the external register, wherein the processing unit, prior to requesting the operand data, continues execution while said read ahead control unit reads the operand data from the external memory and the external register. 21. A memory access control method of controlling memory access from a processor to a memory and a register, comprising the steps of: reading, in advance, operand data from the external memory and the external register in response to a store instruction from the processor and before loading the operand data to the processor from the memory and the register in response to a load instruction from the processor, wherein the processor, prior to issuing the load instruction, executes other instruction codes while reading the operand data from the external memory and the external register, storing the operand data into internal registers, and transferring the operand data to the processor when the load instruction is issued.
