초록 ▼

Described is a removable assembly for use on a fixed surface. The assembly includes a post having a base (42) and an attachment assembly (8). The attachment assembly includes a base plate (10) and a magnet assembly (12), both capable of carrying a magnetic current. The magnet assembly includes a hou

Described is a removable assembly for use on a fixed surface. The assembly includes a post having a base (42) and an attachment assembly (8). The attachment assembly includes a base plate (10) and a magnet assembly (12), both capable of carrying a magnetic current. The magnet assembly includes a housing (20) and a magnet (22) disposed within the housing. To use, the magnet assembly is placed adjacent the base plate, the magnetic forces attracting and holding them together. The magnet is positioned apart from the base plate while the housing contacts the base plate to form the magnet circuit. An attachment plate (30) is connected to the housing upper wall adjacent its outer surface. The attachment plate includes one or more outwardly projecting attachment bolts (26). As assembled, the bolts engage corresponding openings (48) in the post base (42).

대표청구항 ▼

Described is a removable assembly for use on a fixed surface. The assembly includes a post having a base (42) and an attachment assembly (8). The attachment assembly includes a base plate (10) and a magnet assembly (12), both capable of carrying a magnetic current. The magnet assembly includes a hou

Described is a removable assembly for use on a fixed surface. The assembly includes a post having a base (42) and an attachment assembly (8). The attachment assembly includes a base plate (10) and a magnet assembly (12), both capable of carrying a magnetic current. The magnet assembly includes a housing (20) and a magnet (22) disposed within the housing. To use, the magnet assembly is placed adjacent the base plate, the magnetic forces attracting and holding them together. The magnet is positioned apart from the base plate while the housing contacts the base plate to form the magnet circuit. An attachment plate (30) is connected to the housing upper wall adjacent its outer surface. The attachment plate includes one or more outwardly projecting attachment bolts (26). As assembled, the bolts engage corresponding openings (48) in the post base (42). irst yield is applicable to any product chip having the same first critical area curve as the sampled defect data from the first set of selected percentage areas, and predicting a second yield based on the sampled defects from the second set of selected percentage areas, wherein the predicted yield is applicable to any product chip having the same first critical area curve as the sampled defect data from the second set of selected percentage areas. 5. A method as recited in claim 4, further comprising: providing the first and second yields to designers of product chips; and designing a product chip that has the same characteristics as the semiconductor test structures that were sampled to achieve either the first or second yield, whichever is higher. 6. A method as recited in claim 4, further comprising: providing the first and second yields to designers of product chips; and designing a product chip that excludes the same characteristics as the semiconductor test structures that were sampled to achieve either the first or second yield, whichever is lower. 7. A method as recited in claim 1, where the selected percentage areas correspond to a specific number of unit cells of each semiconductor test structure.8. A method as recited in claim 7, wherein each unit cell includes a conductive line that is designed to have a high potential and a conductive line that is designed to have a low potential during a voltage contrast inspection.9. A method as recited in claim 7, wherein each unit cell has a relatively small granularity that is equal to or less than 25 &mgr;m.10. A method as recited in claim 1, wherein a first percentage area of a first semiconductor test structure is sampled for defects and a second percentage area of a second semiconductor test structure is sampled for defects, and wherein the first percentage area differs from the second percentage area.11. A method as recited in claim 10, wherein the semiconductor test structures also include a third, fourth, fifth, sixth, and seventh semiconductor test structure and a third percentage area is sampled from the third semiconductor test structure, a fourth percentage area is sampled from the fourth semiconductor test structure, a fifth percentage area is sampled from the fifth semiconductor test structure, a sixth percentage area is sampled from the sixth semiconductor test structure, and a seventh percentage area is sampled from the seventh semiconductor test structures.12. A method as recited in claim 10, wherein the first semiconductor test structure has a first set of characteristics that differ from a second set of characteristics of the second semiconductor test structures.13. A method as recited in claim 12, where the first and second set of characteristics each include a set of line width and line spacing values.14. A method as recited in claim 1, further comprising: predicting a first yield based on the sampled defects from the first set of selected percentage areas, wherein the first yield is applicable to any product chip having the same first critical area curve as the sampled defect data from the first set of selected percentage areas. 15. A method as recited in claim 14, wherein the semiconductor test structures include random semiconductor test structures that are designed for accurate prediction of the first yield and systematic semiconductor test structures that are designed for accurate prediction of a systematic yield for a same type of structure as the systematic semiconductor test structures, the method further comprising: selectively sampling the systematic semiconductor test structures for defects so that the systematic yield is predicted for selected types of structures; and combining the first yield and the systematic yield into a total yield. 16. A method as recited in claim 14, further comprising providing the total yield to designers of product chips.17. A method as recited in claim 16, further comprising designing a produ