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Method to form copper interconnects by adding an aluminum layer to the copper diffusion barrier

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • H01L-021/44
출원번호 US-0389633 (1999-09-03)
발명자 / 주소
  • Gupta, Subhash
  • Chern, Chyi S.
  • Zhou, Mei Sheng
출원인 / 주소
  • Chartered Semiconductor Manufacturing Ltd.
대리인 / 주소
    Saile, George O.
인용정보 피인용 횟수 : 16  인용 특허 : 9

초록

A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is

대표청구항

A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is

이 특허에 인용된 특허 (9)

  1. McTeer Allen, Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with c.
  2. Kumar Nalin (Austin TX), Diffusion barrier for copper features.
  3. Bai Gang ; Fraser David B., Diffusion barrier for electrical interconnects in an integrated circuit.
  4. Dubin Valery M. ; Shacham-Diamand Yosef ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications.
  5. Lee Chwan-Ying,TWX ; Huang Tzuen-Hsi,TWX, Electroless copper plating method for forming integrated circuit structures.
  6. Nulman Jaim, Method of metalizing a semiconductor wafer.
  7. Jain Ajay, Process for forming a semiconductor device.
  8. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  9. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (16)

  1. Klawuhn, Erich R.; Rozbicki, Robert; Dixit, Girish A., Apparatus and methods for deposition and/or etch selectivity.
  2. Pradhan, Anshu A.; Rozbicki, Robert, Atomic layer profiling of diffusion barrier and metal seed layers.
  3. Shaviv, Roey; Gopinath, Sanjay; Holverson, Peter; Pradhan, Anshu A., Conformal films on semiconductor substrates.
  4. Cheng, Kezia, Copper interconnects having a titanium-platinum-titanium assembly between copper and compound semiconductor.
  5. Liu, Ping-Yin; Chen, Szu-Ying; Wang, Chen-Jong; Huang, Chih-Hui; Huang, Xin-Hua; Chao, Lan-Lin; Tu, Yeur-Luen; Tsai, Chia-Shiung; Chen, Xiaomeng, Hybrid bonding mechanisms for semiconductor wafers.
  6. Beck,Michael, Metal interconnect structure and method.
  7. Kim, Hyung Kyun; Jung, Sung Hoon; Eun, Yong Seok, Method for depositing silicon nitride layer of semiconductor device.
  8. Rozbicki, Robert T.; Danek, Michal; Klawuhn, Erich R., Method of depositing a diffusion barrier for copper interconnect applications.
  9. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing a diffusion barrier for copper interconnect applications.
  10. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing a diffusion barrier for copper interconnect applications.
  11. Nishizawa, Kenichi; Terai, Yasuhiro; Asano, Akira, Noble metal barrier for fluorine-doped carbon films.
  12. Li,Chaoyong; Su,Siaw Suian Sabrina; Mukherjee Roy,Moitreyee; Badam,Ramana Murthy, Process of forming a composite diffusion barrier in copper/organic low-k damascene technology.
  13. Li,Chaoyong; Su,Siaw Suian Sabrina; Mukherjee Roy,Moitreyee; Badam,Ramana Murthy, Process of forming a composite diffusion barrier in copper/organic low-k damascene technology.
  14. Cabral, Jr., Cyril; Dubois, Geraud J. M.; Edelstein, Daniel C.; Nogami, Takeshi; Sanders, Daniel P., Semiconductor interconnect structure having enhanced performance and reliability.
  15. Cabral, Jr., Cyril; Dubois, Geraud Jean-Michel; Edelstein, Daniel C.; Nogami, Takeshi; Sanders, Daniel P., Semiconductor interconnect structure having enhanced performance and reliability.
  16. Edelstein, Daniel C; Nogami, Takeshi, Semiconductor interconnect structure with multi-layered seed layer providing enhanced reliability and minimizing electromigration.
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