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A vehicle tracking unit for a vehicle of a type including at least one vehicle sensor may include a vehicle position determining device, a wireless communications device, and a controller connected to the wireless communications device and the vehicle position determining device for sending vehicle

A vehicle tracking unit for a vehicle of a type including at least one vehicle sensor may include a vehicle position determining device, a wireless communications device, and a controller connected to the wireless communications device and the vehicle position determining device for sending vehicle position information to a monitoring station. Furthermore, the controller may cooperate with the wireless communications device to send an alarm indication alert to the monitoring station based upon the at least one vehicle sensor. Additionally, the controller may stop sending of further alarm indication alerts upon reaching a predetermined number thereof.

대표청구항 ▼

A vehicle tracking unit for a vehicle of a type including at least one vehicle sensor may include a vehicle position determining device, a wireless communications device, and a controller connected to the wireless communications device and the vehicle position determining device for sending vehicle

A vehicle tracking unit for a vehicle of a type including at least one vehicle sensor may include a vehicle position determining device, a wireless communications device, and a controller connected to the wireless communications device and the vehicle position determining device for sending vehicle position information to a monitoring station. Furthermore, the controller may cooperate with the wireless communications device to send an alarm indication alert to the monitoring station based upon the at least one vehicle sensor. Additionally, the controller may stop sending of further alarm indication alerts upon reaching a predetermined number thereof. ; US-6052039, 20000400, Chiou et al.; US-6114940, 20000900, Kakinuma et al.; US-6133806, 20001000, Sheen; US-6137376, 20001000, Imbornone et al.; US-6184845, 20010200, Leisten et al.; US-6307509, 20011000, Krantz a common gate amplifier circuit, with two input terminals—one signal and one control input—and one output terminal, for amplifying said generated oscillating signal from said oscillation generating means, fed into its signal input terminal and transmitted to its output terminal, whereas the control input terminal is controlled by the output signal of said controlling means; and one bias current terminal for the additionally necessary current reference. 9. The circuit according to claim 1 wherein said controlling means comprises an automatic gain control circuit.10. The circuit according to claim 9, implementing said automatic gain controller, comprising: two NMOS transistors and two PMOS transistors, for a self-biased current source; three resistors and three capacitors for filtering, biasing and decoupling purposes; and one further PMOS transistor for supplying the amplifier gain control current. 11. The circuit according to claim 1 wherein said controlling means comprises two signal terminals, one for signal input and the other for signal output.12. The circuit according to claim 1, and as said controlling means comprising: an automatic gain control circuit, with one input and one output terminal, where the input terminal is connected from two other terminals, the input terminal of said driving means together with the output terminal of said amplifying means; and where the output terminal is connected to the control input terminal of said amplifying means. 13. The circuit according to claim 1 wherein said biasing means comprises a dedicated bias circuit block.14. The circuit according to claim 13, implementing said biasing block comprising: two DC-grounded NMOS transistors and three AC-grounded PMOS transistors, forming a system of current mirrors; one further PMOS transistor, working in nonlinear weak inversion mode; one negative feedback resistor; and one AC grounding capacitor. 15. The circuit according to claim 1 wherein said biasing means comprises two bias current output terminals.16. The circuit according to claim 1, and as said biasing means comprising: a biasing circuit block, with two output terminals, one output terminal setting-up the current reference for said driving means and the other output terminal setting-up the current reference for said isolating means. 17. The circuit according to claim 1 wherein said driving means comprises a White cascode buffer circuit.18. The circuit according to claim 17, implementing said White cascode buffer comprising: two DC-grounded NMOS transistors; one cascode NMOS-transistor; two resistors and one White cascode capacitor; and a reference current source for biasing purposes. 19. The circuit according to claim 18, where said White cascode capacitor is effectively minimized, in order to extend the usable frequency range and in order to save chip area.20. The circuit according to claim 19, where said usable frequency range for operation of the circuit is extending from 1 MHz to about 50 MHz.21. The circuit according to claim 1 wherein said driving means comprises one pair of signal terminals and one bias current terminal.22. The circuit according to claim 1, and as said driving means comprising: a White cascode buffer circuit, with one signal input and one signal output terminal, for driving on its output terminal said oscillation generating means to generate said oscillating signal and where the input terminal is firstly connected via said connecting means to the input terminal of said amplifying means and secondly to the input terminal of said controlling means; and one bias current terminal for the additionally necessary current reference. 23. The circuit according to claim 1 wherein said isolating means comprises an output buffer circuit.24. The circuit according to claim 23, implementing said output buffer comprising: two DC grounded NMOS transistors, forming a current mirror circuit; one further NMOS transistor fo