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System, method and computer program product for web-based integrated circuit design

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0818946 (2001-03-28)
발명자 / 주소
  • Lev, Lavi A.
  • Courtright, David A.
  • Knowles, John B.
  • Jones, Darren M.
출원인 / 주소
  • MIPS Technologies, Inc.
대리인 / 주소
    Sterne, Kessler, Goldstein & Fox, P.L.L.C.
인용정보 피인용 횟수 : 55  인용 특허 : 4

초록

A Web-based integrated circuit design system, method and computer program product tool allows design engineers to utilize a well-understood graphical interface (i.e., a Web browser) to access a wealth of data and services. The services and data include competing standard architectures and reference

대표청구항

A Web-based integrated circuit design system, method and computer program product tool allows design engineers to utilize a well-understood graphical interface (i.e., a Web browser) to access a wealth of data and services. The services and data include competing standard architectures and reference

이 특허에 인용된 특허 (4)

  1. Raz Uri, Information transfer systems and method with dynamic distribution of data, control and management of information.
  2. Lawman Gary R. ; Linoff Joseph D. ; Wells Robert W., Method for configuring circuits over a data communications link.
  3. Schwab Barry H., Secure digital interactive system for unique product identification and sales.
  4. Jason H Culler, System and method for adjusting logic synthesis based on power supply circuit models.

이 특허를 인용한 특허 (55)

  1. White,David; Smith,Taber H., Adjustment of masks for integrated circuit fabrication.
  2. Singh, Gunjeet; Joshi, Aman U., Application of a relational database in integrated circuit design.
  3. Balassanian, Edward, Application server.
  4. Balassanian, Edward, Application server facilitating with client's computer for applets along with various formats.
  5. Balassanian, Edward, Application server for delivering applets to client computing devices in a distributed environment.
  6. Balassanian, Edward, Application server for delivering applets to client computing devices in a distributed environment.
  7. Balassanian, Edward, Application server for delivering applets to client computing devices in a distributed environment.
  8. Smith, Taber H.; Mehrotra, Vikas; White, David, Characterization and reduction of variation for integrated circuits.
  9. Smith,Taber H.; Mehrotra,Vikas; White,David, Characterization and reduction of variation for integrated circuits.
  10. White, David; Smith, Taber H., Characterization and verification for integrated circuit designs.
  11. White,David; Smith,Taber H., Characterization and verification for integrated circuit designs.
  12. Weed,Dan, Chip management system.
  13. Suaya, Roberto; Escovar, Rafael; Ortiz, Salvador, Determining mutual inductance between intentional inductors.
  14. Suaya, Roberto; Escovar, Rafael; Ortiz, Salvador, Determining mutual inductance between intentional inductors.
  15. Petunin,Vladimir V.; Pfeil,Charles L.; Starkov,Alexander N.; Natarajan,Venkat; Smith,Edwin Franklin, Distributed autorouting of conductive paths in printed circuit boards.
  16. Selvakumar,Manickam, Distributed web CGI architecture.
  17. Smith,Taber H.; Mehrotra,Vikas; White,David, Dummy fill for integrated circuits.
  18. Smith,Taber H.; Mehrotra,Vikas; White,David, Dummy fill for integrated circuits.
  19. Smith,Taber H.; Mehrotra,Vikas; White,David, Dummy fill for integrated circuits.
  20. White, David, Dummy fill for integrated circuits.
  21. White, David; Smith, Taber H., Electronic design for integrated circuits based on process related variations.
  22. White,David; Smith,Taber H., Electronic design for integrated circuits based on process related variations.
  23. White,David; Smith,Taber H., Electronic design for integrated circuits based process related variations.
  24. Andrew,Felix G. T. I.; Colleran,John D.; Ellison Taylor,Ian M.; Carroll,Mark S., External resource files for application development and management.
  25. Andrew,Felix G. T. I.; Colleran,John D.; Ellison Taylor,Ian M.; Carroll,Mark S., External resource files for application development and management.
  26. Culter,Bradley G., Firmware development within a framework from different design centers depositing component(s) with related contextual and genealogy information in an accessible repository.
  27. Suaya, Roberto, High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate.
  28. Suaya, Roberto, High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate.
  29. Suaya, Roberto, High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate.
  30. Suaya, Roberto, High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate.
  31. Youngman, Todd Jason; Nordman, John Emery, Language and templates for use in the design of semiconductor products.
  32. Koford,James S.; Hamlin,Christopher L., Method and apparatus for implementing a metamethodology.
  33. Donlin, Adam P.; Densmore, Douglas M., Method and apparatus for precharacterizing systems for use in system level design of integrated circuits.
  34. Aitnouri,Elmehdi; Keyes,Edward; Begg,Stephen; Gont,Val; McIntyre,Dale; Ouali,Mohammed; Zavadsky,Vyacheslav, Method and apparatus for reducing redundant data in a layout data structure.
  35. White, David, Method and system for handling process related variations for integrated circuits based upon reflections.
  36. Vergara Escobar, Mario, Method for specification and integration of reusable IP constraints.
  37. Fry,Randall P.; Pierce,Gregory; Lahner,Juergen, Method of associating timing violations with critical structures in an integrated circuit design.
  38. Ginetti, Arnold; Tarroux, Gerard; Pic, Jean-Noel; Arnaud, Olivier; Deshpande, Devendra, Methods and systems for enabling concurrent editing of electronic circuit layouts.
  39. Smith, Taber H.; Mehrotra, Vikas; White, David, Methods and systems for implementing dummy fill for integrated circuits.
  40. Becer, Murat R.; Geada, Joao M.; La France, Lee; Rethman, Nicholas; Shen, Qian, Multi-engine static analysis.
  41. Suaya, Roberto; Escovar, Rafael; Ortiz, Salvador, Mutual inductance extraction using dipole approximations.
  42. Suaya, Roberto; Escovar, Rafael; Ortiz, Salvador, Mutual inductance extraction using dipole approximations.
  43. Suaya,Roberto; Escovar,Rafael; Ortiz,Salvador, Mutual inductance extraction using dipole approximations.
  44. Youngman,Todd Jason; Nordman,John Emery; Senst,Scott T., Rules and directives for validating correct data used in the design of semiconductor products.
  45. Brandt, Wayne D.; Smith, Vernon R.; Earleson, Walt E.; Roth, Michael E.; Herget, Dale B.; Bray, Steven C.; Wulfert, Wayne J.; Morris, Jeffrey S., Software development apparatus with regulated user access.
  46. Suaya, Roberto; Escovar, Rafael, Synthesis strategies based on the appropriate use of inductance effects.
  47. Suaya,Roberto; Escovar,Rafael, Synthesis strategies based on the appropriate use of inductance effects.
  48. Suaya,Roberto; Escovar,Rafael, Synthesis strategies based on the appropriate use of inductance effects.
  49. Veiseh, Nima; Baarman, David W.; Leppien, Thomas Jay, System and markup language for information extraction from stand-alone devices in webspace.
  50. Tsao,Piao Chuo; Feng,Shu Ling; Tseng,Yi Hong, System and method for customized tape-out requests for integrated circuit manufacturing.
  51. Chen,Szu Ping; Tsao,Piao Chuo; Chen,Yu; Wang,Shin Meei, Tape-out form generation methods and systems.
  52. White,David; Smith,Taber H., Test masks for lithographic and etch processes.
  53. Hamlin,Christopher L., Timing abstraction and partitioning strategy.
  54. Becer, Murat R.; Geada, Joao M.; Katz, Isadore T.; La France, Lee, Timing variation characterization.
  55. Smith,Taber H.; Mehrotra,Vikas; White,David, Use of models in integrated circuit fabrication.
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